Latest Posts
The CXL™ Consortium and PCI-SIG® are excited to announce a memorandum of understanding (MOU) between the two organizations.
- Standards & Compliance
- PCIe
- PCI-SIG
- CXL
- PCI Express specification
- CXL Consortium
The upcoming PCIe® 6.0 specification introduces Flow Control Unit (FLIT) encoding, which enables the specification to provide low latency with high efficiency. FLIT mode is adopted for the PCIe 6.0 architecture because error correction needs to operate on fixed sized packets.
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe FEC
- Forward Error Correction
- FLIT
Mohiuddin Mazumder of Intel was honored at this year’s PCI-SIG US DevCon
- Developers Conference
- PCI-SIG DevCon
- PCI-SIG
- PCI Express
Manisha Nilange of Intel was honored at this year’s PCI-SIG US DevCon
- Developers Conference
- PCI-SIG DevCon
- PCI-SIG
- PCI Express
For almost two decades, the PCI Express® (PCIe®) architecture has offered low latency and high bandwidth in support of next generation systems.
- Systems & Applications
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe FEC
- Forward Error Correction
- FLIT
We are starting 2020 with the release of version 0.5 of the PCI Express® (PCIe®) 6.0 specification incorporating the significant member feedback received on version 0.3.
- Standards & Compliance
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe FEC
- Forward Error Correction
- FLIT
- PCI Express specification
We are starting 2020 with the release of version 0.5 of the PCI Express® (PCIe®) 6.0 specification incorporating the significant member feedback received on version 0.3.
- Standards & Compliance
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe FEC
- Forward Error Correction
- FLIT
- PCI Express specification
The Internet of Things (IoT) Industry is rapidly growing in popularity and breadth of applications.
- Systems & Applications
- PCIe
- PCI Express
- PCIe low power
- PCIe form factors
Our PCI-SIG® members have been hard at work. In 2017, we delivered PCI Express® 4.0 with its 16 GT/s, while also diving headfirst into PCI Express 5.0 development – first announced at our annual PCI-SIG DevCon in June 2017.
- Standards & Compliance
- PCI-SIG
- PCIe 5.0
- PCI Express 5.0
- PCIe Bandwidth
Retimers and redrivers have enabled longer physical channels in servers and storage systems since Peripheral Component Interface Express (PCIe®) 3.0 specification was first introduced almost 10 years ago.
- Signal Integrity
- PCIe 5.0
- PCI Express 5.0
- PCIe 4.0
- PCI Express 4.0
- PCIe Retimer
- PCIe Redriver
- PCI Express specification