Board of Directors
Nat Barbiero is a Senior Fellow at Advanced Micro Devices. He has over 25 years of industry experience, mainly at ATI Technologies and AMD. Within AMD, Nat primarily focuses on I/O interconnect architectures. He also contributes to other industry standards groups, in addition to the PCI SIG.
Dr. Debendra Das Sharma is an Intel Senior Fellow and co-GM of Memory and I/O Technologies in the Data Platforms and Artificial Intelligence Group at Intel Corporation. He is a leading expert on I/O subsystem and interface architecture. He is a member of the Board of Directors for the PCI Special Interest Group (PCI-SIG) and a lead contributor to PCIe specifications since its inception. He is a co-inventor and founding member of the CXL consortium and co-leads the CXL Board Technical Task Force. He co-invented the chiplet interconnect standard UCIe and is the chair of the UCIe consortium.Dr. Das Sharma has a bachelor’s in technology (with honors) degree in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur and a Ph.D. in Computer Engineering from the University of Massachusetts, Amherst. He is a frequent keynote speaker in various conferences and a Distinguished Lecturer in leading Universities and IEEE. He has been awarded the Distinguished Alumnus Award from Indian Institute of Technology, Kharagpur in 2019, the Outstanding Engineer Award by IEEE Region 6 in 2021, and the Industrial Pioneer Award by IEEE Circuits and Systems in 2022.
Rick Eads is a principal program manager at Keysight Technologies with expertise in technical/industrial marketing of test and measurement tools and electronic design automation software in the computer, semi-conductor, communications, and storage industries worldwide. Rick’s specialty is precision product and solution definition. He provides technical leadership in driving standards within industry organizations for PCI Express, CCIX, GenZ, OCP, NVM Express, CEI 4.0, IEEE 802.3, ExpressCard, DDR, SATA, and InfiniBand. He markets test and measurement products covering oscilloscopes and associated compliance software tools, vector network analyzers, bit error ratio testers (BERTs) and EDA tools. Rick earned a MBA from the University of Colorado and holds a BSEE from Brigham Young University with an emphasis on digital design and computer architecture. Rick actively contributes to the development of the PCIe physical layer BASE, CEM, and Test specifications and has led electrical Gold Suite testing at PCI-SIG workshops worldwide since 2004.
Steve Glaser is the Principal Engineer of PCI Express Architecture at NVIDIA.
Jon Lewis is a Distinguished Engineer at Dell EMC. During his tenure, he has been involved with the definition and development of networking and interface architecture for client and enterprise equipment. He has focused on interconnect technologies including PCIe, InfiniBand, Ethernet and Fibre Channel. Prior to joining Dell in 2002, Jon worked for Alcatel Network Systems, where he focused on telecommunications systems communication and control. Industry technical involvement includes IEEE 802.3 and OCP NIC 3.0. Jon holds bachelors and masters of electrical engineering degrees from La Tech University.
Jim Panian is a Senior Director, Technical Standards at Qualcomm Technologies, Inc. Jim has worked in the industry for over 35 years. His responsibilities include standards and architecture planning as pertaining to advanced connectivity technologies. Jim also serves on the board of the CCIX Consortium and formerly served on the boards of the PCCA (WTA) and PCMCIA. Jim has worked in the PCI-SIG since 2004, focusing on M.2 card for WWAN and connectivity; protocol and security. Jim earned his B.S. in Electrical Engineering from the University of Pittsburgh in 1984.
Richard Solomon serves as Vice-President of the PCI-SIG. He is the Technical Marketing Manager for Synopsys' DesignWare PCI Express Controller IP, and has been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec. Prior to joining Synopsys, Richard architected and led the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. He has served on the PCI-SIG Board of Directors for over 10 years, and continues to represent Synopsys on wide variety of PCI workgroups. Richard holds a BSEE from Rice University and 26 US Patents, many of which relate to PCI technology.
Dong Wei is an Arm Fellow and Lead Standards Architect of the Architecture and Technology Group in Arm Limited. Dong joined Arm in 2016. He leads the system architecture for the Arm-based server, DPU , PC and Windows IoT systems, covering industry standards such as PCI Express, Trusted Computing, CXL, UEFI, ACPI, DMTF (Redfish, PMCI and SMBIOS), IPMI, NIST, and OCP. He leads the Arm SystemReady program. Dong is a Member Board of Directors at PCI SIG, CXL Consortium, UCIe Consortium and UEFI Forum. He serves as the Chief Executive at UEFI Forum and Secretary at both CXL and UCIe Consortium. He is also a member of the Steering Committee at OCP.
Al Yanes has served as president of the PCI-SIG since 2003 and chairman since 2006 and is a Distinguished Engineer for IBM in the Systems & Technology Division. He has 26 years of experience working with ASIC design in the I/O industry. Yanes holds 25 patents for PCI™ and other I/O technologies. Yanes is a PCI Express® technology expert for the IBM Rochester office and he is involved in I/O design for IBM's Server products. Yanes holds a B.S. in computer engineering from Rensselaer Polytechnic Institute.
Reen Presnell has served as the Executive Director of the PCI-SIG since 2007 and has supported the efforts of the PCI-SIG since 2000. Reen serves on the Board of VTM Group as a Senior Advisor, after serving there for more than 13 years as its CEO, in addition to serving on the Board of VTM’s parent company, Vital Enterprises. Reen holds an MBA in Global Business from University of Portland and an MA in History from the University of Louisiana.