Continuing Virtual Event Success in 2021: PCI-SIG® PCIe® 5.0 Preliminary FYI Workshop recap and Compliance Workshop #116 Preview

  • Posted on: 9 April 2021

With global health and safety concerns related to the Covid-19 pandemic still greatly limiting in-person events in 2021, PCI-SIG® continues to offer compliance workshop opportunities to our members virtually. We kicked off this transition last year with the PCI-SIG Fall Developers Conference and Compliance Workshops #114 and #115. Earlier this year, we also introduced PCIe® 5.0 specification testing with the PCIe 5.0 Preliminary FYI Workshop.

PCI-SIG® Introduces New Automotive Taskforce

  • Posted on: 21 February 2021

As part of our ongoing effort to broaden the adoption and deployment of PCI Express® (PCIe®) technology into diverse industry verticals, the PCI-SIG® Board of Directors recently announced the PCI-SIG Automotive Taskforce. Members are currently using PCIe specifications for automotive applications, and we are evaluating the suitability and potentially enhancing the PCIe specifications for designs in the automotive ecosystem.

Seamless Transition to PCIe® 5.0 Technology in System Implementations Webinar Q&A

  • Posted on: 22 January 2021

With the widespread adoption of compute-intensive workloads – such as artificial intelligence and machine learning – in enterprise and cloud data centers, high-speed, low-latency interconnects like PCI Express® architecture are required to connect high-performance nodes. The upgrade from PCIe® 4.0 to PCIe 5.0 technology doubles the bandwidth from 16GT/s to 32GT/s, but also impacts signal reach and system topology challenges.

PCI-SIG® in 2020: A Year in Review

  • Posted on: 26 December 2020

Despite the many challenges in 2020, we are proud to report that it has been a successful year for, PCI-SIG®.  We continued the momentum started in 2019 with PCIe® 4.0 Compliance Testing, continued work on the PCIe 6.0 specification, and brought our members new ways to engage with virtual workshops and DevCons. Read on for our top milestones from this year.

The PCIe® 6.0 Specification Webinar Q&A: Error Detection and Correction with FEC

  • Posted on: 28 September 2020

The PCI Express® (PCIe®) 6.0 specification will feature two primary mechanisms to correct errors: Forward Error Correction (FEC) and Cyclic Redundancy Check (CRC). Each 256-byte FLIT comprises of 242 bytes of payload which are protected by 8 Bytes of CRC. The 250 bytes of payload and CRC are protected by 6 Bytes of FEC. FEC operates on the principle of sending redundant data that can be deployed to correct some errors at the Receiver while CRC is an error detection code used to detect errors.