With global health and safety concerns related to the Covid-19 pandemic still greatly limiting in-person events in 2021, PCI-SIG® continues to offer compliance workshop opportunities to our members virtually. We kicked off this transition last year with the PCI-SIG Fall Developers Conference and Compliance Workshops #114 and #115. Earlier this year, we also introduced PCIe® 5.0 specification testing with the PCIe 5.0 Preliminary FYI Workshop.
As part of our ongoing effort to broaden the adoption and deployment of PCI Express® (PCIe®) technology into diverse industry verticals, the PCI-SIG® Board of Directors recently announced the PCI-SIG Automotive Taskforce. Members are currently using PCIe specifications for automotive applications, and we are evaluating the suitability and potentially enhancing the PCIe specifications for designs in the automotive ecosystem.
Many online resources cover the history and current state of industry development for the concept that, in Integrity and Data Encryption (IDE), we refer to as a Trusted Execution Environment (TEE).
With the widespread adoption of compute-intensive workloads – such as artificial intelligence and machine learning – in enterprise and cloud data centers, high-speed, low-latency interconnects like PCI Express® architecture are required to connect high-performance nodes. The upgrade from PCIe® 4.0 to PCIe 5.0 technology doubles the bandwidth from 16GT/s to 32GT/s, but also impacts signal reach and system topology challenges.
Despite the many challenges in 2020, we are proud to report that it has been a successful year for, PCI-SIG®. We continued the momentum started in 2019 with PCIe® 4.0 Compliance Testing, continued work on the PCIe 6.0 specification, and brought our members new ways to engage with virtual workshops and DevCons. Read on for our top milestones from this year.
Wow, 2020 sure has transformed the ways we connect, learn and innovate in industries around the world, and in our daily lives! Thanks to the continued support and flexibility of our member companies, PCI-SIG® has been able to continue expanding the PCI Express® (PCIe®) technology ecosystem.
This year has been challenging for us all and we hope that you and your families are staying healthy and safe. Despite the trials that we have faced, PCI-SIG® is adapting our events and workshops to these new times and pressing on in specification development.
The PCI Express® (PCIe®) 6.0 specification will feature two primary mechanisms to correct errors: Forward Error Correction (FEC) and Cyclic Redundancy Check (CRC). Each 256-byte FLIT comprises of 242 bytes of payload which are protected by 8 Bytes of CRC. The 250 bytes of payload and CRC are protected by 6 Bytes of FEC. FEC operates on the principle of sending redundant data that can be deployed to correct some errors at the Receiver while CRC is an error detection code used to detect errors.