For almost two decades, the PCI Express^® (PCIe^®) architecture has offered low latency and high bandwidth in support of next generation systems. To meet the evolving technology industry’s needs, PCIe specification data rates have doubled, while maintaining full backwards compatibility, every three years. This forward trajectory has allowed PCIe specifications to be leveraged in data demanding markets such as Artificial Intelligence (AI), Machine Learning (ML), Internet of Things (IoT), automotive, High Performance Computing (HPC), enterprise, Cloud, PC and more. The upcoming PCIe 6.0 specification provides a data rate of 64 GT/s and delivers both power efficiency and cost-effective performance boosts. The upcoming specification will include various new features that will allow the technology to remain ahead of the curve.

The recent, PCIe 6.0 specification webinar provided a deep dive into the specification’s new features and an overview of the background on the architecture metrics. This blog is a first of a series of blogs that will review the top features coming to PCIe 6.0 architecture, explain how they will impact future-looking markets and answer some of the commonly asked questions that come up.

PAM4 Signaling

One of the new features introduced in PCIe 6.0 is PAM4 (Pulse Amplitude Modulation with 4 levels) signaling. PAM4 will allow the specification’s channel reach to remain similar to what the PCIe 5.0 specification delivers. The signaling will alleviate the channel loss because it runs at half the frequency with two bits per Unit Interval (UI). However, because this specification has three eyes in the same UI, there will be reduced eye height and width. As a result, the Bit Error Rate (BER) will be several levels of magnitude higher with PAM4, leading the specification to adopt Forward Error Correction (FEC).

Error Detection and Correction

In addition to PAM4, the PCIe 6.0 specification includes error assumptions, including correlation between errors on a Lane as well as across Lanes. The First Bit Error Rate (FBER) is the probability of the first bit error occurring at a Receiver in a Link. The BER is a combination of the FBER, the correlation of errors in a lane and the correlation of errors across Lanes. There are two primary mechanisms to correct these aforementioned errors: correction through Forward Error Correction (FEC) and detection of errors by Cyclic Redundancy Check (CRC), resulting in the eventual correction through Link Layer Retry. FEC operates on the principle of sending redundant data that can be deployed to correct some errors at the Receiver. CRC is an error detection code used to authenticate packet transmission between the sender and the receiving end. PCIe 6.0 technology uses a unique approach to remain low-latency through a combination of relatively lower FBER (10^-6) combined with a light-weight, low latency FEC to do the initial correction. A robust CRC then detects any errors left over after correction that results in a link level retry, which is also very low latency. Using both means of correction will allow the PCIe 6.0 specification to achieve low latency with latency reduction in most cases, low complexity, and a low bandwidth overhead. Unlike networking standards that have 100+ nsec of FEC latency, PCIe technology being a load-store protocol, cannot take any latency hit for many applications that rely on it for its low latency, low power and high bandwidth communication.  

FLIT Encoding

The PCIe 6.0 specification uses Flow Control Unit (FLIT) encoding, which enables the specification to provide low latency with high efficiency. Error correction needs to operate on fixed sized packets, which is why FLIT is adopted for PCIe 6.0 architecture. Since error correction happens on FLIT, we have the CRC check as well as Retry at the FLIT level. Once the Link operates in FLIT mode, any speed change to lower data rates will also have to use the same FLIT mode. Thus, once enabled, FLIT mode is followed in the Link, irrespective of the speed. The FLIT mode is a significant departure for the PCIe 6.0 specification, and the improved bandwidth that results from low overhead amortization allows for high bandwidth efficiency, low latency and reduced area.

More Questions About the PCIe 6.0 Specification?

The PCIe 6.0 specification is still under development, now at version 0.5, and is on track for release in 2021. During this time, the specification will improve with support from over 830 PCI-SIG members. The metrics that PCI-SIG aims to achieve for this new specification and every specification—low latency, high bandwidth, efficiency, area, cost and power—will allow future technologies to excel in a variety of markets. To expand the PCIe specification ecosystem in a meaningful and lasting manner, PCI-SIG continues to do its due diligence through analysis, simulations and test silicon characterization to ensure the success of the PCIe 6.0 specification.

Watch the full PCIe 6.0 Specification webinar to learn more about the specification and in-depth questions during the Q&A. Also, stay tuned for the upcoming series of Q&A blogs dedicated to answering the many questions about the new specification’s features that were submitted during the live presentation.