The upcoming PCIe® 6.0 specification introduces Flow Control Unit (FLIT) encoding, which enables the specification to provide low latency with high efficiency. FLIT mode is adopted for the PCIe 6.0 architecture because error correction needs to operate on fixed sized packets.

Mohiuddin Mazumder of Intel was honored at this year’s PCI-SIG US DevCon

Manisha Nilange of Intel was honored at this year’s PCI-SIG US DevCon

As part of our ongoing effort to broaden the adoption and deployment of PCI Express^® (PCIe^®) technology into diverse industry verticals, the PCI-SIG^® Board of Directors recently announced the PCI-SIG Automotive Taskforce.

Is your company interested in speaking at PCI-SIG^® Virtual Developers Conference 2021? The 

Despite the many challenges in 2020, we are proud to report that it has been a successful year for, PCI-SIG^®.  We continued the momentum started in 2019 with PCIe^® 4.0 Compliance Testing, continued work on the PCIe 6.0 specification, and brought our members new ways to engag

Wow, 2020 sure has transformed the ways we connect, learn and innovate in industries around the world, and in our daily lives!

Given the shift to virtual events this year, PCI-SIG^® has adapted to a primarily digital world via various online initiatives like educational webinars, blogs and more.

One of the many new features included in the PCI Express^® (PCIe^®) specification will be PAM4 (Pulse Amplitude Modulation with 4 levels) signaling.

PCI-SIG^® has shifted to virtual events for the 2020 calendar year and our first major members event was the Virtual PCI-SIG Developers Conference.