One of the many new features included in the PCI Express^® (PCIe^®) specification will be PAM4 (Pulse Amplitude Modulation with 4 levels) signaling.

For almost two decades, the PCI Express^® (PCIe^®) architecture has offered low latency and high bandwidth in support of next generation systems.

At this year’s Open Compute Project Global Summit in San Jose on March 4 -5, attendees will have the opportunity to learn how PCI Express^® (PCIe^®) specifications enable OCP systems today and how newer versions of

We are starting 2020 with the release of version 0.5 of the PCI Express^® (PCIe^®) 6.0 specification incorporating the significant member feedback received on version 0.3.

Our PCI-SIG^® members have been hard at work. In 2017, we delivered PCI Express^® 4.0 with its 16 GT/s, while also diving headfirst into PCI Express 5.0 development – first announced at our annual PCI-SIG DevCon in June 2017.

From Israel to Europe and Japan to Taiwan, the PCI-SIG^® Israel, Europe and APAC 2019 Developers Conference tour has come to an end for the year.

PCI Express^® (PCIe^®) technology is deployed worldwide by PCI-SIG member companies, so it only makes sense that PCI-SIG^® travels around the globe too.

Retimers and redrivers have enabled longer physical channels in servers and storage systems since Peripheral Component Interface Express (PCIe^®) 3.0 specification was first introduced almost 10 years ago.

Earlier this month, I attended another eventful Flash Memory Summit (FMS) and I am pleased to say that PCI Express^® (PCIe^®) was around every corner at this year’s event.

This year’s Flash Memory Summit (FMS) is coming up on August 6. As PCI Express technologies continue to evolve and make strides in the industry, PCI-SIG^® is excited to highlight our participation in the growth of flash storage.