The upcoming PCIe® 6.0 specification introduces Flow Control Unit (FLIT) encoding, which enables the specification to provide low latency with high efficiency. FLIT mode is adopted for the PCIe 6.0 architecture because error correction needs to operate on fixed sized packets.

As part of our ongoing effort to broaden the adoption and deployment of PCI Express^® (PCIe^®) technology into diverse industry verticals, the PCI-SIG^® Board of Directors recently announced the PCI-SIG Automotive Taskforce.

Is your company interested in speaking at PCI-SIG^® Virtual Developers Conference 2021? The 

Given the shift to virtual events this year, PCI-SIG^® has adapted to a primarily digital world via various online initiatives like educational webinars, blogs and more.

The PCI Express^® (PCIe^®) 6.0 specification will feature two primary mechanisms to correct errors: Forward Error Correction (FEC) and Cyclic Redundancy Check (CRC). Each 256-byte FLIT comprises of 242 bytes of payload which are protected by 8 Bytes of CRC.

The upcoming PCI Express^® (PCIe^®) 6.0 specification will continue PCI-SIG’s^® longstanding history of innovation for the next generation of products to keep up with evolving needs in a wide range of markets.

One of the many new features included in the PCI Express^® (PCIe^®) specification will be PAM4 (Pulse Amplitude Modulation with 4 levels) signaling.

For almost two decades, the PCI Express^® (PCIe^®) architecture has offered low latency and high bandwidth in support of next generation systems.

Before the emergence of autonomous driving, our cars provided isolation from the outside world. We could move from point A to point B with the press of a pedal and a Mapquest print-out in the passenger seat.

Each year, over 800 PCI-SIG^® member companies are invited to attend the PCI-SIG U.S. Developers Conference.