PCI-SIG Developers Conference Israel 2023 Agenda

Tel Aviv, Israel

Day One - Monday, October 16, 2023
8:30 am – 9:30 am Registration & Breakfast
9:30 am  – 11:00 am  PCI Express Basics & Background 
11:00 am – 12:00 pm PCIe 6.0 Electrical Update 
12:00 pm – 1:00 pm Lunch & Exhibit
1:00 pm – 2:00 pm PCIe CEM Updates
2:00 pm – 3:00 pm PCIe 6.0 Protocol Update 
3:00 pm – 3:30 pm PM Break & Exhibit
3:30 pm – 4:30 pm PCIe 6.0 PHY Logical 
4:30 pm – 5:30 pm PCIe Compliance Updates


Day Two - Tuesday, October 17, 2023                                        
8:30 am – 9:30 am                                       Registration & Breakfast
9:30 am – 10:30 am  Verification of Flit Error Injection in PCIe 6.0
10:30 am – 11:00 am  AM Break & Exhibit
11:00 am – 12:00 pm Troubleshooting Complex LTSSM Corner Cases & Timing
12:00 pm  – 1:00 pm  Lunch & Exhibit 
1:00 pm – 2:00 pm Traffic Generation and Trace Analysis of Select PCIe Features
2:00 pm – 3:00 pm Connector and Cable Assembly Challenges for PCIe 5.0 and 6.0
3:00 pm – 3:30 pm  PM Break & Exhibit 
3:30 pm – 4:30 pm PCIe Retimer Telemetry for RAS on Cloud Compute Systems
4:30 pm – 5:30 pm AI/ML for Autonomous Vehicles with PCIe Technology


Speakers and Abstracts 

Yaron Bar Sinai

As Customer Engineering Senior Director and Israel Site manager, Yaron Bar Sinai has responsibility to understand customers’ needs and convert them into practical implementation at the Chip, FW & SDK levels. Prior to Astera Labs, Yaron served as senior director for customer solution and ASIC Director at Marvell Semiconductor.

PCIe Retimer Telemetry for RAS on Cloud Compute Systems

PCIe is a major interconnect between processors, accelerators, networking, and storage components in hyperscale cloud datacenter systems. The ability to monitor, identify, and fix problems with minimal effect on the end user becomes more and more essential as the speed and number of PCIe links increase. PCIe Retimers are uniquely positioned between Root Complex and Endpoint devices and can thus offer telemetry capabilities to monitor and identify potential failures during system activity.

Attendees will:

• Learn how PCIe Retimers can help identify Link reliability issues at cloud scale.

• Understand which kind of parameters a Retimer can extract from the PCIe Link and interconnect.

• Discover why time stamping is important, and how time stamps are captured.

Paul Cassidy

Paul Cassidy is a Senior R&D Manager for Synopsys’ DesignWare PCI Express Controller IP, based in Dublin, Ireland. With 20 years of industry experience, Paul has worked on the architecture and design of Synopsys PCI Express controller since joining Synopsys in 2009. Paul has a BEng from University College Cork.

PCIe 6.0 Protocol Update

This session covers PCI Express protocol developments over the last year or two, including completed ECNs, selected ECRs under development, and major protocol/spec changes in PCIe 6.0.  Completed ECNs include Combined Power and Relaxed Detect Timing.  Selected ECRs under development include TEE Device Interface Security Protocol (TDISP), DOE 1.1, CMA Update, ATS 2.0, and Unordered I/O (UIO).  Major protocol/spec changes for PCIe 6.0 include Flit Mode, Segment Support in Flit Mode, L0p replacing L0s in Flit Mode, Shared Flow Control Credits, 14-Bit Tags in Flit Mode, Max_Payload_Size enhancements, Deprecated features, and Improved SR-IOV spec integration.

PCIe 6.0 PHY Logical

PCI Express (PCIe) specification has been doubling the data rate every generation in a backwards compatible manner every two to three years. PCIe 6.0 specification has adopted PAM-4 signaling at 64.0 GT/s for maintaining the same channel reach as prior generations. A forward error correction (FEC) mechanism will offset the high BER of PAM-4. A new Flit-based approach with a light-weight, low-latency FEC coupled with a strong CRC and a low-latency link level retry mechanism in PCIe 6.0 specification meets the stringent low-latency, high bandwidth and high reliability goals. Shared credit pooling across multiple virtual channels is included to reduce the area and power overhead while providing the necessary quality of service guarantees. We also present a new low-power state (L0p) that ensures power consumption is proportional to bandwidth usage without impacting the traffic flow.

Vamshi Kandalla

Vamshi brings to GRL a strong track record of success with over 20 years’ experience in the semiconductor and systems industry. Vamshi is the Chief Strategy Officer and leads GRLs strategic and commercial initiatives and has held leadership positions with Applied Micro, MosChip Semiconductor, and Standard Microsystems. for global marketing, product management, technical management and business creation. Vamshi holds a B.E. in Instrumentation Engineering and an MBA.

AI/ML for Autonomous Vehicles with PCIe Technology

The core requirement for expanding AI/ML adoption and usage in Autonomous driving is “Swift, Real Time Data Processing for predictive decision making leading to safe outcomes”. PCIe 6.0 technology with its fast data rates of up to 64 GTs, low latency and additional features that support fast data transfer allow for rapid expansion of AI/ML for Autonomous driving. Key use cases for Autonomous vehicles that need fast data processing are 1) Detection Algorithms 2) Autopilots 3) Digital Cockpit enhancements- Radar Detectors, Heads up display, AI assistants, centralized storage etc. This paper will delve into benefits of PCIe technology for expanding AI/ML for Autonomous driving with use case details, technical drivers and examples.

Isaac Livny

Isaac Livny engaged with PCI Express Technology since its incubation, developing PCIe based networking and communication products and acting as company representative to the PCISIG. Presented in PCISIG DevConn events and participated in PCISIG workgroups. Currently supporting the PCI Express development community worldwide engaging protocol analysis, emulation and compliance tools

Traffic Generation and Trace Analysis of Select PCIe Features

Traffic generation and trace analysis tools can be used to test, validate, and verify operation of PCI Express traffic, highlighting through a selection of PCI express features: Lane margining, data encryption, power management and error messaging. LM command and margin adjustment packets are generated by either configuration transactions or control skips and decoded into LM transactions, and LM requests and responses are collapsed into LM commands. We illustrate IDE Streams established, IDE TLP prefixes added and associated with an IDE Stream, IDE messages sent, and SPDM key management transport protocols implemented. Low power states – We show how low power entry timeout, and T_power_on and T_common mode exit latency measurement. Error messaging tests – we illustrate how errors can be enabled, masked, their severity set, and non-fatal uncorrectable errors reported as advisory correctable errors.

Mohiuddin Mazumder

Mohiuddin Mazumder is a Senior Principal Engineer in Data Center and AI division of Intel. He leads the Electrical pathfinding and Standards development work for high-speed differential interconnect technologies. He co-chairs the PCI-SIG Electrical WG and also leads the PCIe 5.0/6.0 Internal and External Cables specification for 32 and 64 GT/s.

PCIe 6.0 Electrical Update

In this presentation, we will provide an overview of updates to the specification of Reference Clock, Transmitter, Receiver, and Channel Compliance for PCIe 6.0 64 GT/s data rate. We will highlight the key improvements in circuit and channels required for achieving doubling of the data rate over PCIe 5.0.

Manisha Nilange

Manisha Nilange is an IO Architect and Analog Engineering Manager at Intel Corp. She has been with Intel Corp for 17 years. She leads multiple form-factor specification development, transmitter and receiver compliance test methodology and compliance tool development. Manisha chairs the CEM, Mini CEM (M.2) and SFF-8639 Connector (U.2) workgroups in PCI-SIG and co-chairs the Serial Enabling workgroup. Manisha holds MS in Electrical Engineering from the University of Texas at Arlington.

PCIe CEM Updates 

This presentation provides updates on the PCI Express CEM specification development work in the PCI-SIG Electromechanical Workgroup. The presentation focuses on providing an overview of the changes introduced in PCI Express Card Electromechanical Specification, Rev 5.0 (CEM 5.0) and related ECRs. The presentation also provides an overview of several potential improvements under investigation for CEM 6.0. This includes Add-in Card outline updates, sideband interfaces and connector optimizations. 

PCIe Compliance Updates

The PCI-SIG has introduced the 5.0 Integrators List program with a new maximum data rate of 32 GT/s enabling a bi-direction link bandwidth up to 128 GB/s for a x16 link. The PCI Express Architecture PHY Test Specification Rev 5.0 has updated the 16 GT/s tests to support the faster rate and introduced new testing requirements including uncorrelated jitter and pulse width jitter for all 5.0 devices. Discussion of measurement methodologies for Tx Signal Quality and Link Equalization testing will provide insight into the latest measurement methodologies.

Pinal Patel

Pinal is the Associate Director at Einfochips Ltd. He has more than 15 years of experience in architecting the verification environment for SoC and IPs. He has been involved with verifying the PCIe IP since last 10 years. He has worked on all the generations of PCIe starting from 1.0 to 6.0. He has presented technical presentation at PCI-SIG DevCon before.

Verification of Flit Error Injection in PCIe 6.0

Nowadays serial protocols have evolved to get the fastest and fittest throughput. This evolution increases the complexity in any serial protocol’s physical Layer. PCIe 6.0 (64 GTs) has many important features added compared to 5.0. One of them is addition if FLIT concept. Also, they have added Flit Error Injection capability. This capability gives user to introduce error in their transmitted Flit or OS. Because of this they can easily verify or achieve some of the corner cases. So, it becomes important to verify this Flit error injection capability. This presentation talks about the efficacious verification of Flit Error Injection Capability. With the verification approach presented in presentation DUT can be tested vigorously by using CDV (constraint random verification). With approach presented in the presentation many issues were discovered. With the said approach we can reduce the verification time and effort. We also achieved 100% function coverage for the same.

Yamini Shastry

Yamini Shastry is Director of Customer Success, ensuring VIAVI customers are fully supported on the operation and application of VIAVI Xgig® protocol analysis systems. She has extensive software engineering experience, developing analysis solutions for storage and compute markets. Yamini holds a MS degree in Computer Science from the University of New Hampshire.

Troubleshooting Complex LTSSM Corner Cases & Timing

As we move to PCIe 6.0, increased data rates will present even greater interoperability challenges when bringing up links, especially where speed and timing are concerned. During link initiation, link partners follow a complex link training protocol called LTSSM. The protocol includes multiple branching state machines and tight timing constraints. When LTSSM interop issues arise, it can be difficult to replicate them among a myriad of potential causes. This session will provide designers with insight and techniques on troubleshooting these complex transactions with repeatability, including debugging during bringup, and testing boundary conditions with a highly configurable link partner.

Richard Solomon

Richard Solomon is Technical Marketing Manager for Synopsys' PCIe Controller IP.  He’s been involved in PCI chip development since the original PCI spec, co-chairs the PCI-SIG compliance workgroup, and has served on the PCI-SIG Board of Directors for some 20 years. Richard holds a BSEE from Rice University and 27 US Patents, many PCI-related.

PCI Express Basics & Background 

In this session, attendees learn the basics of the PCI Express Architecture. This presentation covers the key features of PCI Express and provides an overview of the Electrical, Packet-based Protocol and Configuration Mechanism of this high-performance serial bus architecture. This session is geared towards attendees new to PCI Express Technologies. 

Lilia Smaoui

Lilia Smaoui joined Rohde&Schwarz over 2 years ago as a product manager in Vector Network Analyzer product division.

She is responsible for VNA automation suite, especially the application of high-speed cable compliance testing. Previously, she gathered experience as system engineer and application engineer at Lantiq and Intel connected home division

Connector and Cable Assembly Challenges for PCIe 5.0 and 6.0

With 32 GT/s in PCIe 5.0 and 64 GT/s in PCIe 6.0, channel characteristics like loss, reflections and crosstalk are increasingly critical for the overall system performance. We will discuss performance requirements and implementations of PCIe 5.0 / 6.0 connectors and cable assemblies and the corresponding test setups and measurement methods to characterize and verify these interconnects. New metrics of ICN and IRL are included, as well as the related measurements. As the PCIe specifications define the performance requirements without the test fixtures, optimized test fixture design and accurate test fixture modelling and de-embedding is key for good measurement results. We will preview modern de-embedding techniques with accurate impedance modelling of lead-ins and lead-outs.