Day One - Wednesday June 12, 2024

Time	Track 1 - PCI Express	Track 2 - PCI-SIG Architecture	Track 3 - Members Implementation	Track 4 - Members Implementation
8:00 am – 9:00 am	Registration in Foyer
9:00 am - 9:30 am	Introductory Keynote / Annual Members Meeting
9:30 am - 10:30 am	PCIe 6.0/7.0 Electrical Update	PCI-SIG Architecture Overview	Impact of UIO ECN on PCIe Controller Design and Performance	Challenges and Insights in Developing a Chiplet Based Retimer
10:30 am - 11:30 am	PCIe CEM Updates	PCI Express Basics	PCIe PTM in Modern Server Systems	Troubleshooting LTSSM Transactions and Timing in PCIe 6.0
11:30 am - 1:00 pm	Lunch and Exhibit
1:00 pm - 2:00 pm	PCIe 6.0/7.0 PHY Logical	PCIe Electrical Basics	PCIe Sideband Bus Transition to I3C	PCI Express 6.0 Protocol Troubleshooting and Debug
2:00 pm - 3:00 pm	PCIe Compliance: Electrical Deep Dive	Marteting Work Group Updates & PCIe Applications Across New Market Segments	Electro-Optic Co-Simulation of High-speed Interconnects	Verification of Flit Performance, Logging and Error Injection
3:00 pm - 3:30 pm	PM Break and Exhibit
3:30 pm - 4:30 pm	PCIe 6.0 Protocol Update	PCI Express M.2/U.2 Updates	PCIe Over Optical: Implementation and Challenges	Demystifying Verification Challenges of TDISP
4:30 pm - 5:30 pm	PCIe Strategic Vision Panel Discussion
5:30 pm - 7:00 pm	PCI-SIG Evening Reception

PCIe 6.0/7.0 Electrical Update  

Wednesday, June 12 | 9:30 AM – 10:30 AM PT

Thursday, June 13 | 9:00 AM – 10:00 AM PT

In this presentation, we will provide an overview of updates to the specification of Reference Clock, Transmitter, Receiver, and Channel Compliance for PCIe 6.0 64 GT/s data rate. We will highlight the key improvements in circuit and channels required for achieving doubling of the data rate over PCIe 5.0.

Speaker: Mohiuddin Mazumder

Mohiuddin Mazumder is a Senior Principal Engineer in Data Center and AI division of Intel. He leads the Electrical Pathfinding and Standards Development work for high-speed differential interconnect technologies. He co-chairs the PCI-SIG Electrical WG and also leads  the PCIe 5.0/6.0 Internal and External Cables specification for 32 and 64 GT/s.

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PCIe CEM Updates

Wednesday, June 12 | 10:30 AM – 11:30 AM PT

Thursday, June 13 | 10:30 AM – 11:30 AM PT

This presentation provides updates on the PCI Express CEM specification development work in the PCI-SIG Electromechanical workgroup. The presentation focuses on providing an overview of the changes introduced in PCI Express Card Electromechanical Specification, Rev 6.0 (CEM 6.0), that includes changes related to the mechanical outline, connector SI, power connectors and sideband signals. The presentation also provides summary of various ECNs approved for Rev 5.0 of the specification. Updates related to the workgroup direction for CEM 7.0 are also included. 

Speaker: Manisha Nilange

Manisha Nilange is a Principal Engineer at Intel Corp. She has been with Intel Corp for 18 years. She leads multiple form-factor specification development, transmitter and receiver compliance test methodology and compliance tool development. Manisha chairs the PCI Express Card Electromechanical (CEM), PCI Express Mini (M.2) and PCI Express SFF Connector (U.2) workgroups in PCI-SIG and co-chairs the Serial Enabling workgroup. Manisha holds MS in Electrical Engineering from the University of Texas at Arlington.

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PCIe 6.0/7.0 PHY Logical

Wednesday, June 12 | 1:00 PM – 2:00 PM PT

PCI Express (PCIe) specification has been doubling the data rate every generation in a backwards compatible manner every two to three years. PCIe 6.0 specification has adopted PAM-4 signaling at 64.0 GT/s for maintaining the same channel reach as prior generations. A forward error correction (FEC) mechanism will offset the high BER of PAM-4. A new Flit-based approach with a light-weight, low-latency FEC coupled with a strong CRC and a low-latency link level retry mechanism in PCIe 6.0 specification meets the stringent low-latency, high bandwidth and high reliability goals. Shared credit pooling across multiple virtual channels is included to reduce the area and power overhead while providing the necessary quality of service guarantees. We also present a new low-power state (L0p) that ensures power consumption is proportional to bandwidth usage without impacting the traffic flow.

Speaker: Debendra Das Sharma

Dr. Debendra Das Sharma is an Intel Senior Fellow and co-GM of Memory and I/O Technologies,  Data Platforms and Artificial Intelligence Group, at Intel Corporation. He is a leading expert on I/O subsystem and interface architecture. He delivers Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCIe), and Intel’s Coherency interconnect, as well as their implementation. 

Dr. Das Sharma is a member of the Board of Directors and treasurer for the PCI Special Interest Group (PCI-SIG). He has been a lead contributor to PCIe specifications since its inception. He is the co-inventor of CXL and a founding member of the CXL consortium. He co-leads the CXL Board Technical Task Force, and is a leading contributor to CXL specifications. He co-invented the chiplet interconnect standard UCIe and is the chair of the UCIe consortium.

Dr. Das Sharma has a bachelor’s in technology (with honors) degree in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur and a Ph.D. in Computer Engineering from the University of Massachusetts, Amherst. He holds 190+ US patents and 500+ patents world-wide. He is a frequent keynote/ plenary speaker, distinguished lecturer, invited speaker, and panelist at the IEEE International Test Conference, IEEE Hot Interconnects, IEEE Cool Chips, IEEE 3DIC, SNIA SDC, PCI-SIG Developers Conference, CXL consortium, Open Server Summit, Open Fabrics Alliance, Flash Memory Summit, Intel Innovation, and Universities (CMU, Texas A&M, Georgia Tech, UIUC, UC Irvine). He has been awarded the Distinguished Alumnus Award from Indian Institute of Technology, Kharagpur in 2019, the IEEE Region 6 Outstanding Engineer Award in 2021, the first PCI-SIG Lifetime Contribution Award in 2022, the IEEE Circuits and Systems Industrial Pioneer Award in 2022, and the IEEE Computer Society Edward J. McCluskey Technical Achievement Award in 2024.

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PCIe Compliance: Electrical Deep Dive

Wednesday, June 12 | 2:00 PM – 3:00 PM PT

The PCI-SIG has introduced the 5.0 Integrators List program with a maximum data rate of 32 GT/s (NRZ). Development of the 6.0 Integrators List program with a new maximum data rate of 64 GT/s (PAM4) enabling a bi-direction link bandwidth up to 256 GB/s for a x16 link is underway. Discussion of measurement methodologies for Tx Signal Quality and Link Equalization will provide insight into the latest techniques as we evolve from NRZ to PAM4 signaling. The foundation established by the PCIe 6.0 Base specification will provide an entry point to our discussion of 64 GT/s methods as we explore the challenges of extending the jitter and voltage measurements to high channel loss scenarios anticipated for CEM and other popular form factors.   

 

Speaker: David Bouse

David Bouse is a Principal Technology Leader at Tektronix with expertise in highspeed SERDES including transmitter and receiver test methodologies, digital signal processing algorithms for NRZ/PAM4 signaling, clock characterization, and automation software architecture. David represents Tektronix within the PCI-SIG and CXL standard bodies contributing to the Electrical and Serial Enabling groups participating in the Base, CEM, and test specification development. Pathfinding is his specialty for stressed eye calibration techniques and transmitter characterization to advance data rate speed/reliability. David leads numerous gold test suites at the PCI-SIG compliance workshops and helps to develop future programs with an emphasis on test and measurement correlation. David supports real time oscilloscope and receiver hardware test development and is the technical leader for the Tektronix PCI Express and CXL solutions. 

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PCIe 6.0 Protocol Update

Wednesday, June 12 | 3:30 PM – 4:30 PM PT

Thursday, June 13 | 2:30 AM – 3:30 PM PT

This session covers PCI Express protocol developments over the last 2+ years, including completed ECNs, selected ECRs under development, and key protocol changes planned for PCIe 7.0.  Completed ECNs include DOE 1.1, Alternative Protocol DLLP Reservation, Unordered I/O (UIO),12V-2x6 Connector Updates, CMA-SPDM Revised, MMIO Mailbox Passthrough (MMPT), Architectural Out-of-Band Management, Removing Prefetchable Terminology, and OHC-E Capability Enumeration.  Selected ECRs under development include Inter-System Bridge (ISB), Address Translation Services (ATS) 1.2 & 2.0, NOP Flit Extensions, and Enhanced SFI (eSFI).    

 

Speaker: Joe Cowan

Joe Cowan is a Senior Systems Architect in Hewlett Packard Enterprise.  He represents HPE in the PCIe Protocol Workgroup, where he's authored numerous ECNs and errata.  During his 45-year career with HP/HPE, Joe has worked in many other areas, including UEC, CXL, Gen-Z, InfiniBand, chipset/platform architecture, OS development, and security.

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PCIe Fundamentals of Equalization

Thursday, June 13 | 11:30 AM – 12:30 PM PT

Link Equalization, enables a component to adjust the settings of its Link partner’s Transmitters, facilitating the improvement of signal quality at the local Receiver. The procedure has continually evolved since its inception to meet industry needs. This presentation will give an overview and cover the requirements of Link Equalization from the perspective of the PHY Logical Layer and it will describe the nuances of the feature that were introduced in each generation of the protocol. In addition, various approaches to executing the equalization procedure, based on implementation requirements, will be discussed.

Speaker: Nat Barbiero

Nat Barbiero is a Fellow at Advanced Micro Devices and has been designing PCI Express physical layer hardware for over 20 years. He has been a member of the PCI SIG since 2005 and he participates in numerous PCI SIG Workgroups. Nat has made significant contributions as a member of the PHY Logical Subteam of the PWG.

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PCIe Strategic Vision Panel Discussion

Wednesday, June 12 | 4:30 PM – 5:30 PM PT

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PCIe Compliance: Protocol Deep Dive

Thursday, June 13 | 1:30 PM – 2:30 PM PT

This presentation discusses the requirements for PCI Express 4.0 and 5.0 Protocol compliance and interoperability. It provides an in-depth review of all Protocol testing performed for the PCIe 4.0 and 5.0 compliance programs—with a focus on requirements for the 5.0 program. Every component of PCIe Protocol compliance is discussed including Link and Transaction Layer, Retimer Logical, Lane Margining, and Configuration testing. This session will also cover the timeline for upcoming Compliance Workshop events worldwide, where members can validate their parts for compliance to the PCI-SIG “Gold” suite of tests. The session will also discuss planned updates for PCIe 6.0 Link and Transaction Layer Compliance Testing. 

Speaker: Gordon Getty

Gordon is Senior Product Marketing Manager at Teledyne LeCroy. He has been working on PCI Express technologies for 23 years. Gordon is an active contributor to the PCI Express Test Specifications. Gordon graduated from Glasgow University with a Bachelor’s degree in Electronics and Music and a MSc in Information Technology from the University of Paisley.

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Track 2 – PCI-SIG Architecture

PCI-SIG Architecture Overview 

Wednesday, June 12 | 9:30 AM – 10:30 AM PT

This presentation provides an overview of PCI™, PCI-X™ and PCI Express. Basic protocol details, and key concepts such as Configuration Space, Message Signaled Interrupts, Transaction Attributes and Split Transactions which span the spectrum from Conventional PCI through PCI-X to PCI Express are explained. This presentation should be a particularly useful starting point for attendees new to PCI-SIG technologies.

Speaker: Richard Solomon

Richard Solomon is Technical Marketing Manager for Synopsys' PCIe Controller IP.  He’s been involved in PCI chip development since the original PCI spec, co-chairs the PCI-SIG compliance workgroup, and has served on the PCI-SIG Board of Directors for some 20 years. Richard holds a BSEE from Rice University and 27 US Patents, many PCI-related.

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PCI Express Basics

Wednesday, June 12 | 10:30 AM – 11:30 AM PT

Thursday, June 13 | 9:00 AM – 10:00 AM PT

In this session, attendees learn the basics of the PCI Express Architecture. This presentation covers the key features of PCI Express and provides an overview of the Electrical, Packet-based Protocol and Configuration Mechanism of this high-performance serial bus architecture. This session is geared towards attendees new to PCI Express Technologies.

Speaker: Richard Solomon

Richard Solomon is Technical Marketing Manager for Synopsys' PCIe Controller IP.  He’s been involved in PCI chip development since the original PCI spec, co-chairs the PCI-SIG compliance workgroup, and has served on the PCI-SIG Board of Directors for some 20 years. Richard holds a BSEE from Rice University and 27 US Patents, many PCI-related.

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PCIe Electrical Basics

Wednesday, June 12 | 1:00 PM – 2:00 PM PT

PCIe Electrical Basics will give the audience an overview of the physical layer specification. We will focus our discussion on target channels central to the base electrical spec development, as well as key transmitter and receiver architecture requirements. We will also discuss in depth the channel compliance simulation methodology enabled by Seasim (Statistical Channel Simulator).

Speaker: Dean Gonzales

Dean Gonzales is an Analog Design Fellow at AMD and is actively involved with circuit architecture analysis, advanced package development, system architecture and signal integrity. Dean has three decades of experience working with top tier companies including Intel, Broadcom and NASA.

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Marketing Work Group Update & PCIe Applications Across New Market Segments

Wednesday, June 12 | 2:00 PM – 3:00 PM PT

For the past 20 years, the PCI Express® (PCIe®) specification had remained ahead of the increasing demand for a high-bandwidth, low-latency interconnect for compute-intensive systems in diverse market segments. In this presentation hosted by PCI-SIG Market Workgroup (MWG) Co-Chair Scott Knowlton, attendees will receive an update about the latest PCI-SIG MWG activities. Additionally, attendees will learn about how PCIe technology is used in multiple market segments like data centers, network edge, telecoms, artificial intelligence, automotive and more. Attendees will also learn about what protocol support and feature trends are being found in these markets.

Speaker: Scott Knowlton

Scott Knowlton is the Director of Strategy in the Synopsys IP Group. He started his career as a chip designer and he has been in Synopsys Marketing since 1997. In 2003, he launched our PCIe IP and began his relationship with PCI-SIG. He has been the co-chair of the MWG since 2018.

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PCI Express M.2/U.2 Updates

Wednesday, June 12 | 3:30 PM – 4:30 PM PT

This presentation provides updates on the PCI Express M.2 and U.2 Specification development work in the PCI-SIG PCIe Mini (M.2) and SFF-8639 (U.2) workgroups resp. The presentation provides a snapshot of the changes that have been incorporated into the latest M.2/U.2 specifications. The presentation will also cover details on approved ECNs since last release of these specifications (Rev 4.0). 

Speaker: Manisha Nilange

Manisha Nilange is a Principal Engineer at Intel Corp. She has been with Intel Corp for 18 years. She leads multiple form-factor specification development, transmitter and receiver compliance test methodology and compliance tool development. Manisha chairs the PCI Express Card Electromechanical (CEM), PCI Express Mini (M.2) and PCI Express SFF Connector (U.2) workgroups in PCI-SIG and co-chairs the Serial Enabling workgroup. Manisha holds MS in Electrical Engineering from the University of Texas at Arlington.

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Update on MiniSAS-HD External Cables

Thursday, June 13 | 10:30 AM – 11:30 AM PT

This presentation will provide an update on the activities within the PCI-SIG Cabling Workgroup. The information in this presentation refers to a specification that is still in the development process. All material is subject to change before specification is released, but does reflect the latest efforts, major milestones, status and projected path forward towards completing the project.

 Speaker: Samuel Kocsis

Sam Kocsis currently holds the role of Director of Standards and Technology at Amphenol, focusing on the proliferation of innovative interconnect solutions. Sam coordinates Amphenol’s engagement strategies in various industry standards and consortiums across networking, server/storage, optics, and commercial markets. He is active in IEEE 802.3, OIF, and OCP projects, and is currently a co-chair of the OSFP MSA and chairman of the PCI-SIG Cabling Workgroup and co-chair of the PCI-SIG Optical Cabling Sub-team. Sam holds BSEE and MSEE degrees from the University of Rochester, in Rochester, New York.

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PCIe 5.0/6.0 Internal and External Cable Specifications

Thursday, June 13 | 11:30 AM – 12:30 PM PT

Speaker: Mohiuddin Mazumder

Mohiuddin Mazumder is a Senior Principal Engineer in Data Center and AI division of Intel. He leads the Electrical Pathfinding and Standards Development work for high-speed differential interconnect technologies. He co-chairs the PCI-SIG Electrical WG and also leads  the PCIe 5.0/6.0 Internal and External Cables specification for 32 and 64 GT/s. 

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Optical PCIe Status

Thursday, June 13 | 1:30 PM – 2:30 PM PT

Speaker: Debendra Das Sharma

Dr. Debendra Das Sharma is an Intel Senior Fellow and co-GM of Memory and I/O Technologies,  Data Platforms and Artificial Intelligence Group, at Intel Corporation. He is a leading expert on I/O subsystem and interface architecture. He delivers Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCIe), and Intel’s Coherency interconnect, as well as their implementation. 

Dr. Das Sharma is a member of the Board of Directors and treasurer for the PCI Special Interest Group (PCI-SIG). He has been a lead contributor to PCIe specifications since its inception. He is the co-inventor of CXL and a founding member of the CXL consortium. He co-leads the CXL Board Technical Task Force, and is a leading contributor to CXL specifications. He co-invented the chiplet interconnect standard UCIe and is the chair of the UCIe consortium.

Dr. Das Sharma has a bachelor’s in technology (with honors) degree in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur and a Ph.D. in Computer Engineering from the University of Massachusetts, Amherst. He holds 190+ US patents and 500+ patents world-wide. He is a frequent keynote/ plenary speaker, distinguished lecturer, invited speaker, and panelist at the IEEE International Test Conference, IEEE Hot Interconnects, IEEE Cool Chips, IEEE 3DIC, SNIA SDC, PCI-SIG Developers Conference, CXL consortium, Open Server Summit, Open Fabrics Alliance, Flash Memory Summit, Intel Innovation, and Universities (CMU, Texas A&M, Georgia Tech, UIUC, UC Irvine). He has been awarded the Distinguished Alumnus Award from Indian Institute of Technology, Kharagpur in 2019, the IEEE Region 6 Outstanding Engineer Award in 2021, the first PCI-SIG Lifetime Contribution Award in 2022, the IEEE Circuits and Systems Industrial Pioneer Award in 2022, and the IEEE Computer Society Edward J. McCluskey Technical Achievement Award in 2024.

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PCIe Firmware Update

Thursday, June 13 | 2:30pm – 3:30 PM PT

This session will provide an overview of the content in the PCI Firmware Specification that is owned and developed by the PCI SIG Firmware and Software Workgroup with active participation of the PCI Community since the PCI SIG creation. In addition, a brief look at what may be the future topics in that workgroup and the future direction of the PCI Firmware Specification.

Speaker: Dong Wei

Dong Wei is an Arm Fellow and Lead Standards Architect of the Architecture and Technology Group in Arm Limited. Dong joined Arm in 2016 after serving Hewlett-Packard Co and HPE for over 21 years. He leads the definition of the hardware and firmware requirements for the Arm A-Profile systems needing to support standard OS images. In addition, he leads the system manageability guidelines for the servers. He covers industry standards for Arm in the areas such as PCIe, Trusted Computing, CXL, UCIe, UEFI, ACPI, DMTF (Redfish, PMCI and SMBIOS), IPMI, NIST, and OCP. He leads the Arm SystemReady program. 

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Track 3 – Members Implementation

Impact of UIO ECN on PCIe Controller Design and Performance 
Wednesday, June 12 | 9:30 AM – 10:30 AM PT

The UIO(Unordered IO) ECN plays a pivotal role in shaping the design and performance of PCIe controllers. In this presentation, we delve into crucial implementation aspects of UIO ECN, focusing on shared flow control. By utilizing a linked list-based receive buffer, we effectively minimize buffer sizes, optimizing resource utilization.
We explore the protocol implications arising from UIO-non-posted and UIO-completion packets. These considerations directly impact latency and buffering, influencing overall system responsiveness. Additionally, we analyze the bandwidth impact of maximal configurations (16-lane) and implementation speeds (1GHz, 2GHz) relative to datapath width (1024-bit, 512-bit). These insights are essential when managing ports within the device application fabric.
A noteworthy shift occurs with the new UIO transactions: ordering requirements move from the fabric to the requester. This paradigm shift holds applicability beyond traditional tree topologies, extending to non-tree architectures.
 

Speaker: Anish Mathew

Anish Mathew, an architect for PCIe IP at Cadence Design Systems, brings extensive expertise in PCIe technology. With a background spanning the 3.0 specification and beyond, Anish has contributed significantly to advancing high-speed interconnects.

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PCIe PTM in Modern Server Systems
Wednesday, June 12 | 10:30 AM – 11:30 AM PT

Precise Time Measurement (PTM) is indispensable for achieving high-accuracy synchronization across diverse components in complex computing systems, enabling more efficient data processing and system coordination. We share insights from implementing PTM in commodity servers and peripheral devices. We discuss the time accuracy achieved and the methods used to quantify them. The quirks of the PCIe specification concerning PTM and Multi-Function Devices are explored, highlighting the challenges faced during implementation. We also delve into the complexities of leveraging PTM in virtualized environments. Finally, we examine the current state of the software ecosystem for PTM enablement and propose future directions for improvement.

Speaker: Wojtek Wasko

Wojtek is a Senior HW Architect at NVIDIA; his job involves creating new HW features and shepherding their enablement in the SW ecosystem. With background in large-scale high-performance computing, his main area of interest are the challenges of efficient time synchronization and its application in modern distributed systems.

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PCIe Sideband Bus Transition to I3C

Wednesday, June 12 | 1:00 PM – 2:00 PM PT

With the growing trend for PCIe and CXL solutions and more sophisticated manageability use cases (attestation, asynchronous notifications, etc.), the newly published PCIe Base Spec 6.2 specification defined an optional backward-compatible upgrade of SMBus sideband management path to I3C. This presentation describes the use cases enabled by the upgrade, especially addressing SMBus limitations noticed by the industry. Intel and Solidigm partnered to implement the first solution of this specification using off-the-shelf components from Aspeed, Renesas, and Microchip and enabling the use of MCTP protocol as per DMTF I3C binding. The experimental results that validate the solution are presented.

Speaker: Janusz Jurski

Janusz Jurski is a platform architect at Intel Corporation. His primary focus is on server systems management. He has more than a decade of experience in this subject area, with multiple contributions to important industry forums and specifications, such as DMTF, PCI-SIG, MIPI, SNIA, and OCP.

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Electro-Optic Co-Simulation of High-speed Interconnects

Wednesday, June 12 | 2:00 PM – 3:00 PM PT

PCI-SIG formed the PCIe over Optics Working Group in 2023 to integrate optical applications, leveraging their extended reach and lower power consumption. With the industry moving to PCIe 7.0 and data rates increasing, there's a growing need for Electro Optical co-simulation and simulation-to-measurement matching, helping ensure system-level PCIe over Optics performance. This presentation explores solutions for this, improving pre-bring up verification and offers insights into optimizing PCIe over Optics performance and ensuring successful technology implementation. The audience will gain insights into tackling challenges in PAM4 electrical-optical-electrical links, equalization requirements for optical impairments, and enabling PCIe technology over optics.

Speaker: Monica Olvera

Monica Olvera is the Product Manager for Synopsys’ high-speed SerDes PHY IP portfolio. She has 7+ years of experience in the field of electrical testing and validation of SerDes IP. She holds a bachelor's degree in engineering from California State Polytechnic University, Pomona.

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PCIe Over Optical: Implementation and Challenges

Wednesday, June 12 | 3:30 PM – 4:30 PM PT

Dive into real examples of running PCIe over optical fiber.  Example will detail multiple implementations of 64Gbps (and slower) data transmissions, BER results, and challenges encountered during implementation.    Tradeoffs for Optical vs Traditional  implementations.  Discussion of challenges, highlights, and potential workarounds for limits of Optical PCIe Protocol including side band signaling, idle handling, and reliability.

Speaker: David Kulanky

David Kulansky is Director of Product Marketing at Alphawave Semi focused on High-Speed IO.  David has 20+ years of semiconductor experience, focused on mastering best fit solutions to streamline new product development.  Before joining Alphawave, David held positions in AMS, RF & SerDes design, but he most recently focused on PCIe & Ethernet solutions. David holds degrees from Princeton University & Johns Hopkins University.

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Demystifying Verification of PCIe 6.0 Equalization

Thursday, June 13 | 9:00 AM – 10:0 AM PT

As PCIe continues to evolve and deliver faster speeds, new challenges emerge on signal distortion with high frequency. Equalization procedure comes to enable components to adjust transmitter and receiver setup to improve the signal quality. This is a crucial process to ensure data integrity and reliable communication between the hardware components. There are several scenarios that are examined on this paper: PAM4 influence, introduction of TS0, introduction of new coefficients, new set of presets, the new ordered sets flow, Equalization checkers and general verification. Insightful information, such as implementation approaches, and robust testing scenarios will be supplied to guarantee the design’s intended functionality.

Speaker: Virgina Silva

Virginia is a PCIe developer at Cadence Design Systems on PCIe Verification IP, with experience in several PCIe domains and specializing in Equalization process. She holds a bachelor’s degree in Control and Automation Engineering from Federal University of Minas Gerais, Brazil. 

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Implementing Virtual Hierarchies

Thursday, June 13 | 10:30 AM – 11:30 AM PT

Modern high-performance devices like SmartNICs and DPUs often present themselves to host systems as virtualized PCIe hierarchies complete with multiple virtual devices, in part to get around the 8 function limit which originated with PCI.  This presentation will cover design options and implementation considerations for a variety of such possible SoC designs and architecture choices to allow effective implementation.  While the focus is on hardware design, software developers may find the topic and design implications to be of interest as well.  

Speaker: Richard Solomon

Richard Solomon is Technical Product Manager for Synopsys' PCIe Controller IP.  He’s been involved in PCI chip development since the original PCI spec, co-chairs the PCI-SIG compliance workgroup, and has served on the PCI-SIG Board of Directors for some 20 years. Richard holds a BSEE from Rice University and 27 US Patents, many PCI-related.

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 PCIe IDE Device Validation and Software Development

Thursday, June 13 | 11:30 AM – 12:30 PM PT

As the adoption of PCIe IDE gains momentum, ensuring comprehensive functionality and compliance with the standard becomes crucial for both device manufacturers and software developers. This presentation explores the utilization of exercisers as a powerful tool for programming and validating PCIe IDE-capable devices, facilitating the development of IDE-enabling software and identifying potential functional gaps in device implementations. Exercisers are specialized tools designed to stress-test and exercise specific features and capabilities of hardware components. In the context of PCIe IDE, exercisers play a vital role in path clearing the PCIe IDE enabling flow and fixing.

Speaker: Jaiprakash Shrivastav

With 13 years of experience in data center server CPU validation at Intel, Jaiprakash Shrivastav is a seasoned system validation engineer. His expertise lies in functional validation of data center server IO functionalities such as PCIe and PCIe IDE.

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Flit Mode Vs Non-Flit Mode Protocol  -  Decoding Analyzer Traces

Thursday, June 13 | 1:30 PM – 2:30 PM PT

With the many changes made to the PCI Express 6.0 Base Specification, correlating the layered, packet-based transactions of non-FLIT protocols to the continuous streaming of 1b/1b encoded FLIT mode messages can be challenging. Side-by-side analyzer trace captures between non-FLIT and FLIT mode protocols will be used to facilitate user adoption from the old layered, packet-based structure of PCI Express to the new performance enhancements of PCIe FLIT mode messaging. This session will demonstrate how TLP and DLLP packets are integrated into the continuous stream of FLIT messages to improve Link speed scalability and reliability into future generations of PCI Express.

Speaker: Rob Vezina

Rob Vezina is a Field Application Engineer with Viavi Solutions. He specializes in the use of PCIe protocol tools for silicon analysis and debugging. Rob graduated with a BASc in Electrical Engineering from the University of Toronto (Canada). He has worked in high speed serial protocol architecture for 20+ years.

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Efficient Verification of PCIe Speed Change Algorithm

Thursday, June 13 | 2:30 PM – 3:30 PM PT

This session describes a case study on complex PCIe speed change mechanisms for Gen1 to Gen6. It also contains challenges and solutions while verifying the PCIe speed change algorithm compared to the legacy testbench. This paper also describes possible error injection to verify the PCIe speed change algorithm fully. With this approach, we can find many corner cases compared to the legacy testbench and hence quality of IP is improved. With this approach, I’m able to achieve all possible speed change scenarios and achieve its coverage successfully. With this approach, the number of required tests to validate the whole speed change mechanism is reduced compared to the legacy testbench.

Speaker: Jaydeep Vezina

Jaydeep has completed his master’s in engineering from GTU. He has been working as an ASIC verification senior engineer in eInfochips an arrow company for the last 5+ years. (Worked on- AHB, USB3.0, Synopsys PCIe-5.95a,Gen1-Gen6, and CXL3.0 protocol) Before joining this organization, he worked in ISRO Space Applications Centre. He has published many papers in SNUG, SIG, DVCon, Devcon, and CDN Live events.

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Track 4 – Members Implementation

Challenges and Insights in Developing a Chiplet Based Retimer 

Wednesday, June 12 | 9:30 AM – 10:30 AM PT

The chiplet era offers superior performance, reduced development time, and cost savings through modular design, ensuring reliability and reusability. Our focus is on chiplet-based PCIe-CXL Retimer products for High-Performance Computing (HPC). Leveraging PCIe's modular architecture, a single PCIe-CXL chiplet is designed and chiplet-based advantages are demonstrated across versatile x4, x8, and x16 Retimer products and future portfolio expansion, meeting and exceeding PCIe-CXL performance metrics. We utilize Kandou's expertise in OIF-CEI-USR Chiplet Chord technology, developing single, dual, and quad-die PCIe/CXL Retimer SoCs. We share insights gained, contributing to chiplet design methodologies for standard package, highlighting challenges in design, test, and productization.

Speaker: Majid Foodeei

Majid Foodeei is Director of Standards at Kandou. During his career, Majid has helped develop and bring to market products from advanced DSP and network processing system-on-chip’s to wired and wireless servers. Majid has several granted patents and numerous publications. Majid holds a Ph.D. in Electrical Engineering, McGill University, Canada.

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Troubleshooting LTSSM Transactions and Timing in PCIe 6.0

Wednesday, June 12 | 10:30 AM – 11:30 AM PT

During link initiation, link partners follow a complex link training protocol called LTSSM.  The protocol includes multiple branching state machines and tight timing constraints. When LTSSM interop issues arise, it can be difficult to replicate them among a myriad of potential causes. PCIe 6.0 introduces FLIT mode negotiations, TS0 and L0p states to LTSSM, and new OS patterns for transitions to/from L0 states. 
This session will provide designers with insight and techniques for troubleshooting these complex transactions with repeatability, including debugging during bring-up and testing boundary conditions with a highly configurable link partner.

Speaker: Yamini Shastry

Yamini Shastry leads the Customer Success team and is responsible for ensuring VIAVI customers are fully supported on the operation and application of VIAVI Xgig protocol analysis systems.  She has years of software engineering experience with expertise in building and delivering test and analysis solutions for high-speed protocols. 

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PCI Express 6.0 Protocol Troubleshooting and Debug

Wednesday, June 12 | 1:00 PM – 2:00 PM PT

The PCI Express 6.0 specification enables many new capabilities including the 64GT/s data rate using PAM4 signaling. These changes require significant changes to the protocol layers to support the new signaling. This presentation will discuss changes to Link Training including Equalization protocol, and also the changes to the Data Link Layer and Transaction Layer when the link is operating in both Flit mode and Non-Flit mode. The presentation will also discuss key techniques to assist in analyzing, troubleshooting and debugging systems and endpoints designed to the PCIe 6.0 specification.

Speaker: Gordon Getty

Gordon is Senior Product Marketing Manager at Teledyne LeCroy. He has been working on PCI Express technologies for 22 years. Gordon is an active contributor to the PCI Express Test Specifications. Gordon graduated from Glasgow University with a Bachelor’s degree in Electronics and Music and a MSc in Information Technology from the University of Paisley. 

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Verification of Flit Performance, Logging and Error Injection

Wednesday, June 12 | 2:00 PM – 3:00 PM PT

Nowadays serial protocols have evolved to get the fastest and fittest throughput. This evolution increases the complexity in any serial protocol’s physical Layer. PCIe GEN6 (64 GTs) has many important features added compared to GEN5. One of them is the addition of FLIT concept. Along with this Base spec has also added Flit Performance, Logging and Error Injection capability. These capabilities give user to measure Flit Performance, Log the different errors received during Flit and introduce error injection on transmitted/Received Flit. Because of this feature in design we can easily measure performance of system , log different error and  verify or achieve some of the corner cases. So, it becomes important to verify this Flit related capabilities. This paper talks about the verification of these Capabilities. With the verification approach presented in paper DUT can be tested vigorously by using CDV (constraint random verification). With approach presented in the paper many issues were discovered. With the said approach we can reduce the verification time and effort. We also achieved 100% function coverage for the same.

Speaker: Pinal Patel

Pinal is the Associate Director at Einfochips Ltd. He has more than 15 years of experience in architecting the verification environment for SoC and IPs. He has been involved with verifying the PCIe IP since last 10 years. He has worked on all the generations of PCIe starting from 1.0 to 6.0. He has presented technical presentation at PCI-SIG DevCon before.

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Demystifying Verification Challenges of TDISP

Wednesday, June 12 | 3:30 PM – 4:30 PM PT

This session aims to address the verification challenges associated with TDISP and proposes methods to simplify them. TDISP Requirements:
1.    Establishing a trust relationship between a TVM and the device.
2.    Securing the PCIe data path between the host and TDI to prevent traffic interception or masquerading on the PCIe fabric.
3.    Securing confidential data of TDI from device controls available to host drivers.
TDISP Verification Scenarios include:
1.    Accessing both TEE_MEM and NON_TEE_MEM in different TDI states and validating all TDISP TLP rules concerning DMA, MSI/MSI-X interrupts.
2.    Exercising multiple VFs connected to TVM and legacy VM by initiating random traffic to access both TEE_MEM & NON_TEE_MEM.
3.    Examining the behavior of TDIs following conventional resets, FLRs, hot plugs, data integrity errors, and a range of other error injection scenarios.
4.    Modifying memory attributes using SET_MMIO_ATTRIBUTE_REQUEST and attempting to access secure data.

Speaker: Tufail Ansari

Tufail Ansari is working as Member Consulting Staff in Questa Verification IP team of Siemens EDA. He has completed his B.Tech in Electronics and Communication Engineering from Delhi Technological University. He has 7 years of working experience in PCIe Gen4, 5, 6 VIPs and working in PCIe security feature from past 3 years.

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Scaling Multi-rack GPU Clustering with Active PCIe Cabling

Thursday, June 13 | 9:00 AM – 10:0 AM PT

The surge in AI workloads demands high-bandwidth, low-latency active PCIe cabling solutions to link larger GPU clusters across multiple racks. The session will highlight the new opportunities for PCIe cabling solutions in disaggregated systems and compare the trade-offs for system implementation decisions.

Attendees will gain insights into:

Treatment of side-band PCIe signals for external cable applications
Clock topology considerations, including pros/cons of distributing REFCLK between systems via external PCIe cables
Implementation details and benefits related to aggregation of multiple PCIe links in a single cable assembly
Implementation details and benefits of in-band telemetry

Speaker: Casey Morrison

As Chief Product Officer of Astera Labs, Casey Morrison plays a pivotal role in product definition and integration into customer systems, specializing in high-speed serial interface design and data interconnect optimization. Having delivered numerous presentations at PCI-SIG DevCons and webinars, Casey's contributions continue to shape the future of connectivity solutions.

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Preparing for PCIe Electrical Measurements Beyond 64GT/s

Thursday, June 13 | 10:30 AM – 11:30 AM PT

With 128 GT/s, PCIe 7.0 will again double the data rate. Keeping PAM4, it will also double the physical bandwidth. To accurately test the performance at this link speed, the measurement path from the test equipment to the pin will need to be accurately characterized up to very high frequencies, so that it can be de-embedded from the measurement results. We will discuss related challenges for test board design and the recommendations of IEEE Std 370 for accurate test fixture characterization and de-embedding as well as practical implementation examples for similar measurement paths. We’ll also take a close look at best practices to accurately characterize the lead-in / lead-out at these frequencies and the significance of impedance corrected de-embedding.

Speaker: Martin Stumpf

Martin Stumpf is Segment Manager for High-Speed Digital Test at Rohde & Schwarz. He joined Rohde & Schwarz in 1990 as R&D engineer and has worked in research & development, project management, product management, regional support and business development. Martin holds an EE degree from Technical University of Munich.

 

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Empirical BER Characterization of Intra-Pair Skew at 64GT/s

Thursday, June 13 | 11:30 AM – 12:30 PM PT

PCIe gen6 adoption of PAM4 signaling comes with a 9.5dB signal-to-noise ratio impact over PCIe gen5 NRZ, thereby increasing the sensitivity to intra-pair skew on Bit Error Ratio (BER). This presentation shows a novel & reliable method for introducing granular intra-pair skew into a given PCIe gen6 interconnect channel with the use of a Bit Error Ratio Tester (BERT). Initial results show the impact of intra-pair skew can be up to 1 order of magnitude on resulting BER. Additionally, the interaction between intra-pair skew and other parameters (such as DMI, SJ, ISI, and EQ) are explo

Speaker: Drew Childress

Drew has a twenty-year career focused around high speed serial PHYs and channels. His last ten years has been supporting BERT technology for NRZ and PAM4.

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Implementation of CMA/SPDM for PCI IDE Security

Thursday, June 13 | 1:30 PM – 2:30 PM PT

This paper elaborates how to implement the Security Protocol and Data Model (SPDM) flow using Data Object Exchange (DOE) for PCIe.
Requirement of SPDM
1.    Provide a robust method to securely exchange keys between devices, which is necessary for encrypting TLPs.
2.    Prevent hackers from intercepting data by encrypting IDE-KM and TDISP packets over an unsecured DOE channel.
SPDM Flow Using DOE
1.    Establish a secure medium of key exchange before TLP encryption. Also, configure the TEE setup using the TDISP protocol.
2.    Establish a secure session with both symmetric and asymmetric methods.
3.    Perform device identification and encrypt secured SPDM packets using cryptographic algorithms, such as digital signatures and key scheduling algorithms.

Speaker: Suprio Biswas

Suprio Biswas is working as Lead Member Technical Staff in Questa Verification IP team of Siemens EDA. He has completed his B.Tech in Electronics and Communication Engineering from Netaji Subhas Institute of Technology. He has 4 years of working experience in PCIe Gen5 and 6 VIPs.