PCI-SIG Developers Conference Korea 2024 Agenda

Seoul, South Korea

September 26, 2024
8:00 am – 9:00 am Registration 
9:00 am  – 10:30 am  PCI Express Basics & Background 
10:30 am – 11:00 AM Break
11:00 am – 12:00 pm PCIe 6.0 Electrical Update
12:00 pm – 1:00 pm Lunch 
1:00 pm – 2:00 pm PCIe CEM Updates
2:00 pm – 3:00 pm PCIe 6.0 Protocol Update 
3:00 pm – 3:30 pm PM Break 
3:30 pm – 4:30 pm PCIe 6.0 PHY Logical 
4:30 pm – 5:30 pm PCIe Compliance Updates

Speakers and Abstracts 

Joe Cowan

Joe Cowan is a Senior Systems Architect in Hewlett Packard Enterprise.  He represents HPE in the PCIe Protocol Workgroup, where he's authored numerous ECNs and errata.  During his 44-year career with HP/HPE, Joe has worked in many other areas, including CXL, Gen-Z, InfiniBand, chipset/platform architecture, OS development, and security.

PCIe 6.0 Protocol Update

This session covers PCI Express protocol developments over the last year or two, including completed ECNs, selected ECRs under development, and key protocol/spec changes envisioned for PCIe 7.0.  Completed ECNs include Relaxed Detect Timing, TDISP, DOE 1.1, Alternative Protocol DLLP Reservation, and Unordered I/O (UIO).  Selected ECRs under development include Sideband Signals, CMA-SPDM, 12V2x6 Connector Updates, MMIO Mailbox Passthrough (MMPT), OHC-E Capability Enumeration, Inter-System Bridge (ISB), ATS 2.0, and Remote Memory Operations (RMOps). 

PCIe 6.0 PHY Logical

PCI Express (PCIe) specification has been doubling the data rate every generation in a backwards compatible manner every two to three years. PCIe 6.0 specification has adopted PAM-4 signaling at 64.0 GT/s for maintaining the same channel reach as prior generations. A forward error correction (FEC) mechanism will offset the high BER of PAM-4. A new Flit-based approach with a light-weight, low-latency FEC coupled with a strong CRC and a low-latency link level retry mechanism in PCIe 6.0 specification meets the stringent low-latency, high bandwidth and high reliability goals. Shared credit pooling across multiple virtual channels is included to reduce the area and power overhead while providing the necessary quality of service guarantees. We also present a new low-power state (L0p) that ensures power consumption is proportional to bandwidth usage without impacting the traffic flow.


Mohiuddin Mazumder

Mohiuddin Mazumder is a Senior Principal Engineer in Data Center and AI division of Intel. He leads the Electrical pathfinding and Standards development work for high-speed differential interconnect technologies. He co-chairs the PCI-SIG Electrical WG and also leads the PCIe 5.0/6.0 Internal and External Cables specification for 32 and 64 GT/s

PCIe 6.0 Electrical Update

In this presentation, we will provide an overview of updates to the specification of Reference Clock, Transmitter, Receiver, and Channel Compliance for PCIe 6.0 64 GT/s data rate. We will highlight the key improvements in circuit and channels required for achieving doubling of the data rate over PCIe 5.0.


Manisha Nilange

Manisha Nilange is an IO Architect and Analog Engineering Manager at Intel Corp. She has been with Intel Corp for 17 years. She leads multiple form-factor specification development, transmitter and receiver compliance test methodology and compliance tool development. Manisha chairs the CEM, Mini CEM (M.2) and SFF-8639 Connector (U.2) workgroups in PCI-SIG and co-chairs the Serial Enabling workgroup. Manisha holds MS in Electrical Engineering from the University of Texas at Arlington.

PCIe CEM Updates 

This presentation provides updates on the PCI Express CEM specification development work in the PCI-SIG Electromechanical Workgroup. The presentation focuses on providing an overview of the changes introduced in PCI Express Card Electromechanical Specification, Rev 5.0 (CEM 5.0) and related ECRs. The presentation also provides an overview of several potential improvements under investigation for CEM 6.0. This includes Add-in Card outline updates, sideband interfaces and connector optimizations. 

PCIe Compliance Updates

The PCI-SIG has introduced the 5.0 Integrators List program with a new maximum data rate of 32 GT/s enabling a bi-direction link bandwidth up to 128 GB/s for a x16 link. The PCI Express Architecture PHY Test Specification Rev 5.0 has updated the 16 GT/s tests to support the faster rate and introduced new testing requirements including uncorrelated jitter and pulse width jitter for all 5.0 devices. Discussion of measurement methodologies for Tx Signal Quality and Link Equalization testing will provide insight into the latest measurement methodologies.

Richard Solomon

Richard Solomon is Technical Marketing Manager for Synopsys' PCIe Controller IP.  He’s been involved in PCI chip development since the original PCI spec, co-chairs the PCI-SIG compliance workgroup, and has served on the PCI-SIG Board of Directors for some 20 years. Richard holds a BSEE from Rice University and 27 US Patents, many PCI-related.

PCI Express Basics & Background 

In this session, attendees learn the basics of the PCI Express Architecture. This presentation covers the key features of PCI Express and provides an overview of the Electrical, Packet-based Protocol and Configuration Mechanism of this high-performance serial bus architecture. This session is geared towards attendees new to PCI Express Technologies.