PCI-SIG Developers Conference Taiwan 2023 Agenda

Taipei, Taiwan

Day One - Monday, February 20, 2023
8:00 am – 9:00 am Registration 
9:00 am  – 10:30 am  PCI Express Basics & Background (Richard Solomon) 
10:30 am – 11:00 am AM Break & Exhibit
11:00 am – 12:00 pm PCIe Compliance Updates (Manisha Nilange)
12:00 pm – 1:00 pm Lunch & Exhibit
1:00 pm – 2:00 pm PCIe PLL Measurement Case Study (John Calvin)
2:00 pm – 3:00 pm  PCI Express Protocol Compliance Troubleshooting and Debug (Gordon Getty)
3:00 pm – 3:30 pm PM Break & Exhibit
3:30 pm – 4:30 pm PCIe 6.0 Protocol Update (Paul Cassidy)
4:30 pm – 5:30 pm  Equalization Implementation Note for PCIe 3.0/4.0/5.0/6.0 (Jebaselvi Johnson) 


Day Two - Tuesday, February 21, 2023                                        
8:00 am – 8:30 am Exhibit
8:30 am – 9:30 am PCIe 6.0 Electrical Update (Mohiuddin Mazumder)
9:30 am – 10:30 am  Designing for Effective Use of PCIe 6.0 Bandwidth (Richard Solomon)
10:30 am – 11:00 am AM Break & Exhibit
11:00 am  – 12:00 pm  PCIe CEM Updates (Manisha Nilange)
12:00 pm – 1:00 pm  Lunch & Exhibit 
1:00 pm – 2:00 pm Connector and Cable Assembly Challenges for PCIe 5.0 and 6.0 (Bryant Hsu) 
2:00 pm – 3:00 pm PCIe 6.0 PHY Logical (Paul Cassidy)
3:00 pm – 3:30 pm  PM Break & Exhibit 
3:30 pm – 4:30 pm Efficacious Verification of Flit Error Injection in PCIe 6.0 (Pinal Patel) 
4:30 pm – 5:30 pm Data Driven Insights Into Stressed Eye Solution Space (Bibin Joshy) 


Speakers and Abstracts 

John Calvin – John Calvin is a Senior Internet Infrastructure and IP Wireline Solutions Product Planner with Keysight Technologies. John manages instrument and solution definitions that address new and emerging needs for both software and instrumentation in the expanding Datacenter field. He is currently a contributing member to IEEE TC10, IEEE 802.3, OIF-CEI, InfiniBand Trade Association and PCI-Express.

PCIe PLL Measurement Case Study

Acquiring a high speed data signal at its full bandwidth and extracting the spectrum through a digital down conversion process permits high performance base-band jitter and phase noise analysis through an all-digital process, which allows direct spectral measurements with high precision.   This presentation will examine a case study and comparison of PCIe PLL measurement methods, it’s history and relative importance as an interoperability indicator.  

Paul Cassidy – Paul Cassidy is a Senior R&D Manager for Synopsys’ DesignWare PCI Express Controller IP, based in Dublin, Ireland. With 20 years of industry experience, Paul has worked on the architecture and design of Synopsys PCI Express controller since joining Synopsys in 2009. Paul has a BEng from University College Cork.

PCIe 6.0 Protocol Update

This session covers PCI Express protocol developments over the last year or two, including completed ECNs, selected ECRs under development, and major protocol/spec changes in PCIe 6.0.  Completed ECNs include Combined Power and Relaxed Detect Timing.  Selected ECRs under development include TEE Device Interface Security Protocol (TDISP), DOE 1.1, CMA Update, ATS 2.0, and Unordered I/O (UIO).  Major protocol/spec changes for PCIe 6.0 include Flit Mode, Segment Support in Flit Mode, L0p replacing L0s in Flit Mode, Shared Flow Control Credits, 14-Bit Tags in Flit Mode, Max_Payload_Size enhancements, Deprecated features, and Improved SR-IOV spec integration.

PCIe 6.0 PHY Logical

PCI Express (PCIe) specification has been doubling the data rate every generation in a backwards compatible manner every two to three years. PCIe 6.0 specification has adopted PAM-4 signaling at 64.0 GT/s for maintaining the same channel reach as prior generations. A forward error correction (FEC) mechanism will offset the high BER of PAM-4. A new Flit-based approach with a light-weight, low-latency FEC coupled with a strong CRC and a low-latency link level retry mechanism in PCIe 6.0 specification meets the stringent low-latency, high bandwidth and high reliability goals. Shared credit pooling across multiple virtual channels is included to reduce the area and power overhead while providing the necessary quality of service guarantees. We also present a new low-power state (L0p) that ensures power consumption is proportional to bandwidth usage without impacting the traffic flow.

Gordon Getty – Gordon is Technical Marketing Manager at Teledyne LeCroy. He has been working on PCI Express technologies for 21 years. Gordon is an active contributor to the PCI Express Test Specifications. Gordon graduated from Glasgow University with a Bachelor’s degree in Electronics and Music and a MSc in Information Technology from the University of Paisle.

PCI Express Protocol Compliance Troubleshooting and Debug

This presentation discusses the requirements for PCI Express 4.0 and 5.0 Protocol compliance and how to debug and investigate issues that commonly arise during testing. Every component of PCIe Protocol compliance is discussed including Link and Transaction Layer, Retimer Logical, Lane Margining, and Configuration testing. Protocol Testing covers many different areas of the specification but many common issues can be resolved by paying attention to certain key areas prior to testing at a Compliance Workshop, helping to avoid delays in getting the device included on the Integrators List.

Bryant Hsu – Bryant Hsu is Product Manager in Business Development & Marketing Department at Rohde & Schwarz Taiwan. He has 5 years R&D experiences before joining Rohde & Schwarz in 2011 and over 10 years test & measurement background which covers signal integrity for high speed interface testing. Bryant holds a MS degree from National Sun Yat-Sen University, Taiwan.

Connector and Cable Assembly Challenges for PCIe 5.0 and 6.0

With 32 GT/s in PCIe 5.0 and 64 GT/s in PCIe 6.0, channel characteristics like loss, reflections and crosstalk are increasingly critical for the overall system performance. We will discuss performance requirements and implementations of PCIe 5.0 / 6.0 connectors and cable assemblies and the corresponding test setups and measurement methods to characterize and verify these interconnects. New metrics of ICN and IRL are included, as well as the related measurements. As the PCIe specifications define the performance requirements without the test fixtures, optimized test fixture design and accurate test fixture modelling and de-embedding is key for good measurement results. We will preview modern de-embedding techniques with accurate impedance modelling of lead-ins and lead-outs.

Jebaselvi Johnson – Jebaselvi is the Sr.Technical Director with PrimeSOC technologies. She has 22+ years of experience in developing digital controllers for ASIC/FPGA with wide industry experience into developing of Interface protocols like PCIE/MIPI/CXL/UCIE. Architect/Designer for front end activities in semiconductor design/verification/validation domains.

Equalization Implementation Note for PCIe 3.0/4.0/5.0/6.0

Equalization across various generations of PCIe will be discussed in this presentation. Equalization phases, bypass, no equalization, algorithm behind equalization setting selections, equalization handling for downstream, upstream, Rx equalization, reflection on transmitter pins and much more. Case study done to show the EQ negotiations for Downstream/Upstream ports connected for communication that supports different max data rates. This presentation also briefs about TS0's introduced in PCIe 6.0 -accomplishment in equalization.

Bibin Joshy – Bibin Joshy works with Tektronix India as a Design Engineer in the Rx Solution space for the past 4 years. He has made significant contributions to developing receiver applications for PCIe (4.0,5.0,6.0), USB4, and TBT4 technologies. He is very passionate about debugging and resolving Issues related to receiver testing.

Data Driven Insights Into Stressed Eye Solution Space

The PCI Express Physical Layer Electrical testing requires testing receiver performance using a worst-case transmitter and channel. Establishing this "Stressed Eye Signal" involves a complex calibration procedure quantified with an eye diagram measurement using the latest DSP techniques. The final step in this calibration starts with nominal stress levels and requires adjustment of cross talk, modeled with Differential Mode Interference or DMI, and Sinusoidal Jitter (SJ) to fine tune the eye within a tight tolerance. Legacy data rates have relied on DMI and SJ to impact the vertical and horizontal eye closure respectively. New interactions and dependencies at 32 GT/s have led to a pronounced interdependence impacting the methods used to achieve this signal. This presentation will analyze empirical data to provide insight into the shape of the solution space and guidance for future development at 64 GT/s.

Mohiuddin Mazumder – Mohiuddin Mazumder is a Senior Principal Engineer in Data Center and AI division of Intel. He leads the Electrical pathfinding and Standards development work for high-speed differential interconnect technologies. He co-chairs the PCI-SIG Electrical WG and also leads the PCIe 5.0/6.0 Internal and External Cables specification for 32 and 64 GT/s.

PCIe 6.0 Electrical Update

In this presentation, we will provide an overview of updates to the specification of Reference Clock, Transmitter, Receiver, and Channel Compliance for PCIe 6.0 64 GT/s data rate. We will highlight the key improvements in circuit and channels required for achieving doubling of the data rate over PCIe 5.0.

Manisha Nilange  – Manisha Nilange is an I/O Architect, focusing on electrical compliance and enabling. She led development of PCIe 2.0 and 3.0 compliance test fixtures and subsequent industry enabling. Manisha has been with Intel Corporation since receiving her MS in Electrical Engineering from the University of Texas, Arlington.

PCIe CEM Updates 

This presentation provides updates on the PCI Express CEM specification development work in the PCI-SIG Electromechanical Workgroup. The presentation focuses on providing an overview of the changes introduced in PCI Express Card Electromechanical Specification, Rev 5.0 (CEM 5.0) and related ECRs. The presentation also provides an overview of several potential improvements under investigation for CEM 6.0. This includes Add-in Card outline updates, sideband interfaces and connector optimizations. 

PCIe Compliance Updates

The PCI-SIG has introduced the 5.0 Integrators List program with a new maximum data rate of 32 GT/s enabling a bi-direction link bandwidth up to 128 GB/s for a x16 link. The PCI Express Architecture PHY Test Specification Rev 5.0 has updated the 16 GT/s tests to support the faster rate and introduced new testing requirements including uncorrelated jitter and pulse width jitter for all 5.0 devices. Discussion of measurement methodologies for Tx Signal Quality and Link Equalization testing will provide insight into the latest measurement methodologies.

Pinal Patel – Pinal is the Associate Director at Einfochips Ltd. He has more than 15 years of experience in architecting the verification environment for SoC and IPs. He has been involved with verifying the PCIe IP since last 10 years. He has worked on all the generations of PCIe starting from 1.0 to 6.0. He has presented technical presentation at PCI-SIG DevCon before.

Efficacious Verification of Flit Error Injection in PCIe 6.0​

Nowadays serial protocols have evolved to get the fastest and fittest throughput. This evolution increases the complexity in any serial protocol’s physical Layer. PCIe 6.0 (64 GTs) has many important features added compared to 5.0. One of them is addition if FLIT concept. Also, they have added Flit Error Injection capability. This capability gives user to introduce error in their transmitted Flit or OS. Because of this they can easily verify or achieve some of the corner cases. So, it becomes important to verify this Flit error injection capability. This presentation talks about the efficacious verification of Flit Error Injection Capability. With the verification approach presented in presentation DUT can be tested vigorously by using CDV (constraint random verification). With approach presented in the presentation many issues were discovered. With the said approach we can reduce the verification time and effort. We also achieved 100% function coverage for the same.

Richard Solomon – Richard Solomon is Technical Marketing Manager for Synopsys' PCIe Controller IP.  He’s been involved in PCI chip development since the original PCI spec, co-chairs the PCI-SIG compliance workgroup, and has served on the PCI-SIG Board of Directors for some 20 years. Richard holds a BSEE from Rice University and 27 US Patents, many PCI-related.

PCI Express Basics & Background 

In this session, attendees learn the basics of the PCI Express Architecture. This presentation covers the key features of PCI Express and provides an overview of the Electrical, Packet-based Protocol and Configuration Mechanism of this high-performance serial bus architecture. This session is geared towards attendees new to PCI Express Technologies. 

Designing for Effective Use of PCIe 6.0 Bandwidth

PCI Express 6.0 introduced 64GT/s signaling, bringing maximum PCIe bandwidth up to 256GB/s!  The sheer amount of data movement now possible offers architectural challenges beyond those arising “simply” from the doubling of clock speed or datapath width.  This presentation will discuss design choices and practices needed to make full use of that bandwidth across a variety of design points from x1 to x16 for both Endpoint and Root Port designs.  Various potential pitfalls and performance scenarios will be covered and data presented from actual early implementations. This presentation should be of interest to both experienced and new PCI Express designers.