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At this year’s PCI-SIG® US Developers Conference 2024, held on June 12-13 in Santa Clara, CA, the PCI-SIG Board of Directors recognized Gordon Getty of Teledyne LeCroy as the recipient of the 2024 Chairperson’s Award for h
- Industry Events
- Compliance
- PCIe 6.0 specification
- Developers Conference

PCI-SIG® is excited to invite members back to our annual PCI-SIG U.S. Developers Conference (DevCon) in the Santa Clara Convention Center in Santa Clara, CA from June 13-14.
- PCI-SIG Membership
- Developers Conference
- PCI-SIG DevCon
- PCI-SIG
- PCI-SIG Membership

The PCI-SIG® Developers Conference returned to Taipei, Taiwan for the first time since 2019 on Feb. 20-21 at the Taipei Marriott Hotel. With 674 total attendees, it was the highest-ever turnout for a DevCon.
- Standards and Compliance
- Developers Conference
- PCI-SIG DevCon
- PCI-SIG Compliance
- PCI-SIG Integrators List

Around the World with PCI-SIG: Join Us at the 2022 International DevCons
By Richard Solomon, PCI-SIG Vice President and Developers Conference Chair
- Standards and Compliance
- Developers Conference
- PCI-SIG DevCon
- PCI-SIG
- PCI-SIG Membership

By Scott Knowlton and Mihaela Erler, PCI-SIG MWG Co-Chairs
- Standards & Compliance
- Developers Conference
- PCI-SIG DevCon
- PCI-SIG
- PCI-SIG Membership

The PCI-SIG® Board of Directors honored three individuals for their years of service and contributions to the development and expansion of PCI Express® (PCIe®) technology during the PCI-SIG US DevCon 2022 on June 21-22 in
- Standards & Compliance
- Developers Conference
- PCI-SIG DevCon
- PCI-SIG
- PCI-SIG Membership

During the PCI-SIG® US DevCon 2022, the PCI-SIG Board of Directors surprised two individuals for their years of service and contributions to the development and expansion of PCI Express® (PCIe®) technology.
- Standards & Compliance
- Developers Conference
- PCI-SIG DevCon
- PCIe 6.0
- PCI Express 6.0
- PCI Express specification

Infographic of the PCIe 6.0 Architecture
- Standards & Compliance
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe Storage
- PCI Express specification
- FLIT
- Forward Error Correction

The upcoming PCIe® 6.0 specification introduces Flow Control Unit (FLIT) encoding, which enables the specification to provide low latency with high efficiency. FLIT mode is adopted for the PCIe 6.0 architecture because error correction needs to operate on fixed sized packets.
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe FEC
- Forward Error Correction
- FLIT

Mohiuddin Mazumder of Intel was honored at this year’s PCI-SIG US DevCon
- Developers Conference
- PCI-SIG DevCon
- PCI-SIG
- PCI Express