One of the many new features included in the PCI Express^® (PCIe^®) specification will be PAM4 (Pulse Amplitude Modulation with 4 levels) signaling.

One of the many new features included in the PCI Express^® (PCIe^®) specification will be PAM4 (Pulse Amplitude Modulation with 4 levels) signaling.

For almost two decades, the PCI Express^® (PCIe^®) architecture has offered low latency and high bandwidth in support of next generation systems.

For almost two decades, the PCI Express^® (PCIe^®) architecture has offered low latency and high bandwidth in support of next generation systems.

PCI Express^® (PCIe^®) technology is the most important high-speed serial bus in servers. Due to its high bandwidth and low latency characteristics, PCI Express architecture is widely used in various server interconnect scenarios, such as:

We are starting 2020 with the release of version 0.5 of the PCI Express^® (PCIe^®) 6.0 specification incorporating the significant member feedback received on version 0.3.

We are starting 2020 with the release of version 0.5 of the PCI Express^® (PCIe^®) 6.0 specification incorporating the significant member feedback received on version 0.3.

Our PCI-SIG^® members have been hard at work. In 2017, we delivered PCI Express^® 4.0 with its 16 GT/s, while also diving headfirst into PCI Express 5.0 development – first announced at our annual PCI-SIG DevCon in June 2017.

I’m pleased to share that PCI-SIG^® continues to make great progress on the development of our next generation of PCIe^® technology – the 

I’m pleased to share that PCI-SIG^® continues to make great progress on the development of our next generation of PCIe^® technology – the