Author’s Note: This blog discusses new functionality introduced in the PCIe 6.0 specification, but please note that subsequent revisions have been published. Developers should always work from the latest revision to ensure they see all specification errata.

PCI-SIG^® has shifted to virtual events for the 2020 calendar year and our first major members event was the Virtual PCI-SIG Developers Conference.

At this year’s Open Compute Project Global Summit in San Jose on March 4 -5, attendees will have the opportunity to learn how PCI Express^® (PCIe^®) specifications enable OCP systems today and how newer versions of

I’m pleased to share that PCI-SIG^® continues to make great progress on the development of our next generation of PCIe^® technology – the 

The SD Association (SDA) recently announced SD Express, which adds the PCI Express^® and NVMe™ interfaces to the SD interface. The PCIe^® interface delivers transfer rates up to 985 megabytes per second (MB/s) and supports backward compatibility with existing SD hosts.

I am happy to share that PCI-SIG^® has begun developing the PCI Express^® (PCIe^®) 6.0 specification, targeted for release in 2021.

On January 22, 2019, the U.S. Cybersecurity and Infrastructure Security Agency issued an emergency directive to mitigate DNS infrastructure tampering intended to disrupt and redirect government and business communications.

At PCI-SIG, we take pride in ensuring that our specifications operate without a hitch. However, sometimes PCI Express developers need to submit Engineering Change Requests (ECRs) to update parts of the specification so that PCIe integrated products can reach their optimal functionality.

By now, you probably know about the PCI-SIG Developers Conference which we hold in Santa Clara each year – a free event for our 750+ member companies with four tracks of presentations over two days.

I’m looking forward to attending the Flash Memory Summit (FMS) next week in Santa Clara.