Specifications

PCI-SIG specifications define standards driving the industry-wide compatibility of peripheral component interconnects. Members regularly review them, providing commentary and change requests when necessary. These requests are considered by technical workgroups and applied as appropriate, resulting in collaboratively devised specifications benefiting millions of platforms and add-in devices.

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Specifications Library

Technology: PCI Express
Specification Title Spec Rev Document Type Release Date
Manufacturer Test Mode Pin ECN
High Volume Manufacturing (HVM) and other manufactur...view more High Volume Manufacturing (HVM) and other manufacturer test processes benefit from the ability to set Add-in Card (AIC) modes that enable multiplexing of standard connector pins for test specific use. This ECR defines a method to allow the system to enable a Manufacturer Test Mode (MFG) on the AIC through the standard interface connector prior to shipping the AIC. This ECR to the CEM specification is consistent with Manufacturing Mode ECN to the SFF-8639 specification. show less
4.x ECN
PCI Express Card Electromechanical Specification Revision 4.0, Version 1.0 (Clean)
This specification is a companion for the PCI Expres...view more This specification is a companion for the PCI Express® Base Specification, Revision 4.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications. show less
4.x Specification
PCI Express Card Electromechanical Specification Revision 4.0, Version 1.0 (Change Bar)
This specification is a companion for the PCI Expres...view more This specification is a companion for the PCI Express® Base Specification, Revision 4.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications. show less
4.x Specification
Errata for the PCI Express Base Specification Revision 4.0
Final Release against Base Revision 4.0 ...view more Final Release against Base Revision 4.0 show less
4.x Errata
PCI Express Architecture Configuration Space Test Specification Revision 4.0, Version 1.0
This document primarily covers PCI Express testing o...view more This document primarily covers PCI Express testing of all defined PCI Express device types and RCRBs for the standard Configuration Space mechanisms, registers, and features in Chapter 6 of the PCI Local Bus Specification (Base 3.x or earlier only) and Chapters 7, 9 (Base 4.x or later only), 10 (Base 4.x or later only) of the PCI Express Base Specification (some additional tested registers are described in other specifications that are referenced in the individual test description). This specification does not describe the full set of PCI Express tests for these devices. show less
4.x Specification
PCI Express Architecture Link Layer and Transaction Layer Test Specification Revision 4.0, Version 1.0
This test specification primarily covers testing of ...view more This test specification primarily covers testing of PCI Express® Device and Port types for compliance with the link layer and transaction layer requirements of the PCI Express Base Specification. Device and Port types that do not have a link (e.g., Root Complex Integrated Endpoints, Root 10 Complex Event Collectors) are not tested under this test specification. While the test environment can accommodate the presence of a Retimer, it will not test the Retimer itself. At this point, this test specification does not describe the full set of PCI Express tests for all link layer or transaction layer requirements. show less
4.x Specification
PCI Express Architecture PHY Test Specification Revision 4.0, Version 1.0
This document provides test descriptions for PCI Exp...view more This document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices. show less
4.x Specification
ACS Enhanced Capabilities ECN
This ECN defines four new services under ACS for Dow...view more This ECN defines four new services under ACS for Downstream Ports, primarily to address issues when ACS redirect mechanisms are used to ensure that DMA Requests from Functions under the direct control of VMs are always routed correctly to the Translation Agent in the host. Three of the services provide redirect or blocking of Upstream Memory Requests that target areas not covered by other ACS services. The fourth service enables the blocking of Upstream I/O Requests, addressing a concern with VM-controlled Functions maliciously sending I/O Requests. show less
4.x ECN
Enhanced PCIe Precision Time Measurement (ePTM) ECN
This ECN effects the PCI Express Base Specification,...view more This ECN effects the PCI Express Base Specification, Version 4.0. ePTM is an improvement on the existing Precision Time Measurement capability that provides improved detection and handling of error cases. ePTM quickly identifies and resolves errors that may cause clocks to become desynchronized. show less
4.x ECN
Async Hot-Plug Updates ECN
This ECN updates several areas related to hot-plug f...view more This ECN updates several areas related to hot-plug functionality, mostly related to Async hot-plug, which is now growing in importance due to its widespread use with NVMe SSDs. All new functionality is optional. This ECN affects the PCIe 4.0 Base Specification. show less
4.x ECN
Errata for the PCI Express® Base Specification Revision 4.0 4.x Errata
Root Complex Event Collector Bus Number Association ECN
This ECN enhances Root Complex Event Collectors (RCE...view more This ECN enhances Root Complex Event Collectors (RCECs) to allow them to be associated with Devices located on additional Bus numbers. show less
4.x ECN
Address Translation Relaxed Ordering ECN
This ECN allows Address Translation Requests and Com...view more This ECN allows Address Translation Requests and Completions to support the Relaxed Ordering bit, where are currently defined to be Reserved for these types of TLPs. The proposal preserves interoperability with older Translation Agents. show less
4.x ECN
PCIe Link Activation ECN
Link Activation allows software to temporarily disab...view more Link Activation allows software to temporarily disable Link power management, enabling the avoidance of the architecturally mandated stall for software-initiated L1 Substate exits. show less
4.x ECN
PCI Express® Base Specification Revision 4.0, Version 1.0
This specification describes the PCI Express® archit...view more This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. show less
4.x Specification
PCI Express® Base Specification Revision 4.0, Version 1.0 (Change Bar)
This specification describes the PCI Express® archit...view more This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. show less
4.x Specification
Expansion ROM Validation ECN
Provide an optional mechanism to indicate to softwar...view more Provide an optional mechanism to indicate to software the results of a hardware validation of Expansion ROM contents. show less
4.x ECN