PCI-SIG specifications define standards driving the industry-wide compatibility of peripheral component interconnects. Members regularly review them, providing commentary and change requests when necessary. These requests are considered by technical workgroups and applied as appropriate, resulting in collaboratively devised specifications benefiting millions of platforms and add-in devices.
Engineering Change Request Process
PCI-SIG members may submit requests to change specifications here. The Engineering Change Request process and form can be found here.
Purchasing Specifications
PCI-SIG members may access specifications online, at no cost, using the Specification Library. Members may filter their search by technology type, revision, and the type of document. Select the appropriate filters and then select the Filter button to initiate your search. Alternatively, members may purchase a hard copy of the specifications, at a reduced member rate, here.
Non-members who are interested in purchasing specifications may submit their order here.
PCI Code & ID Assignment Specifications
The PCI Code & ID Assignment Specifications are accessible to non-members without charge here. PCI-SIG members can download these specifications directly from the Specifications Library below.
This specification provides additional capabilities ...view moreThis specification provides additional capabilities for PCI Express® (PCIe) Add-in Cards (AIC) within the existing framework of legacy system board form factors such as AGP and PCI. The PCI Express solution space was historically confined to Advanced Technology eXtended (ATX) or ATX-based form factors but is now integrated into a broader range of applications. The Balanced Technology Extended (BTX) Interface Specification is acknowledged as another form factor. Other connector and form factors that use PCI Express® signaling, are addressed in separate specifications.
show less
This is a companion specification to the PCI Express...view moreThis is a companion specification to the PCI Express Base Specification. The primary focus of this specification is the implementation of cabled PCI Express® . No assumptions are made regarding the implementation of PCI Express-compliant Subsystems on either side of the cabled Link (PCI Express Card Electromechanical (CEM), ExpressCard™, ExpressModule™, PXI Express™, or any other form factor). Such form factors are covered in separate specifications.
show less
The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution. One of the goals for M.2 is to be significantly smaller in the XYZ and overall volume than the HalfMini Card for the very thin computing Platforms (e.g., Notebook, Tablet/Slate Platforms) that require a much smaller solution.
show less
This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 5.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.
show less
The primary objectives of this External Cable Specif...view moreThe primary objectives of this External Cable Specification for PCI Express 5.0 and 6.0 document are to provide
• 32.0 GT/s and 64.0 GT/s electrical specifications for mated cable assembly and mated cable connector based on SFF-TA-1032 Specification,
• specifications of sideband functions for sideband pins allocated in the SFF-TA-1032 Specification, and
• guidelines for 32.0 GT/s and 64.0 GT/s electrical spec compliance testing.
show less
The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in
both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution.
show less
The primary objectives of this Internal Cable Specif...view moreThe primary objectives of this Internal Cable Specification for PCI Express 5.0 and 6.0 document are to provide 32 GT/s and 64 GT/s electrical specifications for mated cable assembly and mated cable connector based on SFF-TA-1016 Specification, specifications of sideband functions for sideband pins allocated in the SFF-TA-1016 Specification, and guidelines for 32 GT/s and 64 GT/s electrical spec compliance testing.
show less
This test specification is intended to confirm if a ...view moreThis test specification is intended to confirm if a stand-alone Retimer is compliant to the PCIe Base Specification. This test specification is not intended to test Retimers based only on the Extension Devices ECN to the PCI Express Base Specification, Revision 3.x. This test specification only covers stand-alone Retimers in common clock mode, and is not intended to test Retimers integrated onto a platform or an add-in card.
show less
The focus of this specification is on PCI Express® (...view moreThe focus of this specification is on PCI Express® (PCIe®) solutions utilizing the SFF-8639 (also known as U.2) connector interface. Form factors include, but are not limited to, those described in the SFF-8201 Form Factor Drive Dimensions Specification. Other form factors, such as PCI Express Card Electromechanical are documented in other independent specifications.
show less
This document defines the “base” specification for t...view moreThis document defines the “base” specification for the PCI Express architecture, including the electrical, protocol, platform architecture and programming interface elements required to design and build devices and systems. A key goal of the PCI Express architecture is to enable devices from different vendors to inter-operate in an open architecture, spanning multiple market segments including clients, servers, embedded, and communication devices. The architecture provides a flexible framework for product versatility and market differentiation.
show less
This document defines the “base” specification for t...view moreThis document defines the “base” specification for the PCI Express architecture, including the electrical, protocol, platform architecture and programming interface elements required to design and build devices and systems. A key goal of the PCI Express architecture is to enable devices from different vendors to inter-operate in an open architecture, spanning multiple market segments including clients, servers, embedded, and communication devices. The architecture provides a flexible framework for product versatility and market differentiation.
show less
This specification contains the Class Code and Capab...view moreThis specification contains the Class Code and Capability ID descriptions originally contained the
PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and
maintain. This specification also consolidates Extended Capability ID assignments from the PCI
Express Base Specification and various other PCI specifications.
It is intended that this document be used along with the PCI Express Base Specification Revision
5.0.
show less
This Card Electromechanical (CEM) specification is a...view moreThis Card Electromechanical (CEM) specification is a companion for the PCI Express® Base Specification, Revision 5.0. Its primary focus is the implementation of an evolutionary strategy with earlier PCI™ desktop/server mechanical and electrical specifications.
show less
This Card Electromechanical (CEM) specification is a...view moreThis Card Electromechanical (CEM) specification is a companion for the PCI Express® Base Specification, Revision 5.0. Its primary focus is the implementation of an evolutionary strategy with earlier PCI™ desktop/server mechanical and electrical specifications.
show less
This document defines the “base” specification for t...view moreThis document defines the “base” specification for the PCI Express architecture, including the electrical, protocol, platform architecture and programming interface elements required to design and build devices and systems. A key goal of the PCI Express architecture is to enable devices from different vendors to inter-operate in an open architecture, spanning multiple market segments including clients, servers, embedded, and communication devices. The architecture provides a flexible framework for product versatility and market differentiation.
show less
This document defines the “base” specification for t...view moreThis document defines the “base” specification for the PCI Express architecture, including the electrical, protocol, platform architecture and programming interface elements required to design and build devices and systems. A key goal of the PCI Express architecture is to enable devices from different vendors to inter-operate in an open architecture, spanning multiple market segments including clients, servers, embedded, and communication devices. The architecture provides a flexible framework for product versatility and market differentiation.
show less
The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution.
show less
This specification contains the Class Code and Capab...view moreThis specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. It is intended that this document be used along with the PCI Express Base Specification Revision 5.0.
show less
The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution.
show less
The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution.
show less
This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the
programming interface required to design and build systems and peripherals that are compliant with the PCI Express
Specification. This document defines the “base” specification for the PCI Express architecture, including the electrical, protocol,
platform architecture and programming interface elements required to design and build devices and systems.
show less
This is a change bar version of the PCI Express Base...view moreThis is a change bar version of the PCI Express Base 6.0 Specification comparing Base 6.0/1.0 to Base 6.0.1/1.0
show less
This test specification is intended to confirm if a ...view moreThis test specification is intended to confirm if a stand-alone Retimer is compliant to the PCI Base Specification.
show less
This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 5.0.
show less
This document primarily covers PCI Express testing o...view moreThis document primarily covers PCI Express testing of all defined Device Types and RCRBs for the standard Configuration Space mechanisms, registers, and features.
show less
This test specification primarily covers testing of ...view moreThis test specification primarily covers testing of PCI Express® Device and Port types for compliance with the link layer and transaction layer requirements of the PCI Express Base Specification.
show less
This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0.
show less
There are two informative "changebar" versions of th...view moreThere are two informative "changebar" versions of the PCI Express Base 6.0 Specification comparing Base 6.0/1.0 to Base 6.0/0.9 and comparing Base 5.0 to Base 6.0.
show less
This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. This document defines the “base” specification for the PCI Express architecture, including the electrical, protocol, platform architecture and programming interface elements required to design and build devices and systems.
show less
This specification contains the Class Code and Capab...view moreThis specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications.
It is intended that this document be used along with the PCI Express Base Specification Revision 5.0.
show less
This Card Electromechanical (CEM) specification is a...view moreThis Card Electromechanical (CEM) specification is a companion for the PCI Express® Base Specification, Revision 5.0. Its primary focus is the implementation of an evolutionary strategy with earlier PCI™ desktop/server mechanical and electrical specifications.
show less
This Card Electromechanical (CEM) specification is a...view moreThis Card Electromechanical (CEM) specification is a companion for the PCI Express® Base Specification, Revision 5.0. Its primary focus is the implementation of an evolutionary strategy with earlier PCI™ desktop/server mechanical and electrical specifications.
show less
The focus of this specification is on PCI Express® (...view moreThe focus of this specification is on PCI Express® (PCIe®) solutions utilizing the SFF-8639 connector interface. Form factors include, but are not limited to, those described in the SFF-8201 Form Factor Drive Dimensions Specification. Other form factors, such as PCI Express Card Electromechanical are documented in other independent specifications.
show less
This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.
show less
This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.
show less
The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution.
show less
The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution.
show less
This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices
show less
This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices
show less
This document is a companion specification to the PC...view moreThis document is a companion specification to the PCI Express Base Specification and other PCI Express® documents listed in Section 1.1. The primary focus of the PCI Express OCuLink Specification is the implementation of internal and external small form factor PCI Express connectors and cables. This form factor supports multiple market segments, from client, mobile, server, datacenter, and storage. This specification discusses cabling and connector requirements to meet the 8.0 GT/s signaling needs in the PCI Express Base Specification.
show less
This is a companion specification to the PCI Express...view moreThis is a companion specification to the PCI Express Base Specification. The primary focus of this specification is the implementation of cabled PCI Express®. No assumptions are made regarding the implementation of PCI Express-compliant Subsystems on either side of the cabled Link (PCI Express Card Electromechanical (CEM), ExpressCard™, ExpressModule™, PXI Express™, or any other form factor). Such form factors are covered in separate specifications
show less
This is a companion specification to the PCI Express...view moreThis is a companion specification to the PCI Express Base Specification. The primary focus of this specification is the implementation of cabled PCI Express®. No assumptions are made regarding the implementation of PCI Express-compliant Subsystems on either side of the cabled Link (PCI Express Card Electromechanical (CEM), ExpressCard™, ExpressModule™, PXI Express™, or any other form factor). Such form factors are covered in separate specifications
show less
This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.
show less
This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.
show less
This specification contains the Class Code and Capab...view moreThis specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications.
show less
This is a companion specification to the PCI Exp...view moreThis is a companion specification to the PCI Express Base Specification. The primary focus of this specification is the implementation of cabled PCI Express®. No assumptions are made regarding the implementation of PCI Express-compliant Subsystems on either side of the cabled Link (PCI Express Card Electromechanical (CEM), ExpressCard™, ExpressModule™, PXI Express™, or any other form factor). Such form factors are covered in separate specifications.
show less
DISCLAIMER: Table A-1, Bytes 0 to 1...view moreDISCLAIMER: Table A-1, Bytes 0 to 127 (Lower Memory Fields), contained an error in the 1.0 Specification. Byte 0, Identifier, was 0Eh and has been changed to 1Ch.
show less
This specification is a companion for the PCI Expres...view moreThis specification is a companion for the PCI Express® Base Specification, Revision 4.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications.
show less
This specification is a companion for the PCI Expres...view moreThis specification is a companion for the PCI Express® Base Specification, Revision 4.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications.
show less
This document primarily covers PCI Express testing o...view moreThis document primarily covers PCI Express testing of all defined PCI Express device types and RCRBs for the standard Configuration Space mechanisms, registers, and features in Chapter 6 of the PCI Local Bus Specification (Base 3.x or earlier only) and Chapters 7, 9 (Base 4.x or later only), 10 (Base 4.x or later only) of the PCI Express Base Specification (some additional tested registers are described in other specifications that are referenced in the individual test description). This specification does not describe the full set of PCI Express tests for these devices.
show less
This test specification primarily covers testing of ...view moreThis test specification primarily covers testing of PCI Express® Device and Port types for compliance with the link layer and transaction layer requirements of the PCI Express Base Specification. Device and Port types that do not have a link (e.g., Root Complex Integrated Endpoints, Root 10 Complex Event Collectors) are not tested under this test specification. While the test environment can accommodate the presence of a Retimer, it will not test the Retimer itself. At this point, this test specification does not describe the full set of PCI Express tests for all link layer or transaction layer requirements.
show less
This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.
show less
The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution.
show less
There are four informative ...view moreThere are four informative "changebar" versions of the PCI Express Base 5.0 Specification comparing Base 5.0/1.0 to Base 5.0/0.9 and comparing Base 4.0 and Base 5.0. HTML and PDF versions are provided. Both versions are derived from common source material but have different characteristics, and readers may wish to reference both. These documents are non-normative - the NCB PCI Express Base Specification Revision 5.0, Version 1.0 (NCB-PCI_Express_Base_5.0r1.0-2019-05-22.pdf) is the normative version of this specification.
show less
This specification describes the PCI Express archite...view moreThis specification describes the PCI Express architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
show less
The focus of this specification is on PCI Express (P...view moreThe focus of this specification is on PCI Express (PCIe®) solutions utilizing the SFF-8639 connector interface. Form factors include, but are not limited to, those described in the SFF-8201 Form Factor Drive Dimensions Specification. Other form factors, such as PCI Express CEM are documented in other independent specifications.
show less
This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
show less
This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
show less
The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini 3 Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in 4 both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and 5 higher integration of functions onto a single form factor module solution.
show less
The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini 3 Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in 4 both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and 5 higher integration of functions onto a single form factor module solution.
show less
This specification defines an implementation for sma...view moreThis specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified subset of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 2.0. Where this specification 5 does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs.
show less
This specification defines an implementation for sma...view moreThis specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified subset of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 2.0. Where this specification 5 does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs.
show less
This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
show less
This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
show less
This document is a companion Specification to the PC...view moreThis document is a companion Specification to the PCI Express Base Specification and other PCI Express® 2 documents listed in Section 1.1. The primary focus of the PCI Express OCuLink Specification is the implementation 3 of internal and external small form factor PCI Express® connectors and cables optimized for the client and mobile 4 market segments. This Specification discusses cabling and connector requirements to meet the 8.0 GT/s signaling 5 needs in the PCI Express Base Specification. 6
No assumptions are made regarding the implementation of PCI Express compliant components on either side of 7 the Link; such components are addressed in other PCI Express Specifications.
show less
This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express systems in a host computer.
show less
The M.2 form factor is used for Mobile Add-In cards....view moreThe M.2 form factor is used for Mobile Add-In cards. The M.2 is a natural transition from the Mini Card and Half-Mini Card to a smaller form factor in both size and volume. The M.2 is a family of form factors that will enable expansion, contraction, and higher integration of functions onto a single form factor module solution.
show less
This specification is a companion for the PCI Expres...view moreThis specification is a companion for the PCI Express Base Specification, Revision 3.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications. Access Test Channel S-Parameters.
show less
This test specification primarily covers tests of PC...view moreThis test specification primarily covers tests of PCI Express platform firmware for features critical to PCI Express. This specification does not include the complete set of tests for a PCI Express System.
show less
This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building add-in cards or system boards to the PCI Express Card Electromechanical Specification 3.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.
show less
This document primarily covers PCI Express testing o...view moreThis document primarily covers PCI Express testing of all defined PCI Express Device Types and RCRBs for the standard Configuration Space mechanisms, registers, and features in Chapter 6 of the PCI Local Bus Specification and Chapter 7 of the PCI Express Base Specification (some additional tested registers are described in other specifications that are referenced in the individual test description).
show less
This test specification primarily covers testing of ...view moreThis test specification primarily covers testing of PCI Express Device and Port types for compliance with the link layer and transaction layer requirements of the PCI Express Base Specification. Device and Port types that do not have a link (e.g., Root Complex Integrated Endpoints, Root Complex Event Collectors) are not tested under this test specification. At this point, this test specification does not describe the full set of PCI Express tests for all link layer or transaction layer requirements.
show less
The PCI Express 3.0 describes a method to simulate 8...view moreThe PCI Express 3.0 describes a method to simulate 8GT/s channel compliance using a statistical data eye simulator. To help members perform this simulation, a free open source tool called Seasim is provided below. This tool has been tested by members of the Electrical Working Group on multiple channels and has reached version 0.54 which should be useful for members designing 8GT/s systems.
show less
This document primarily covers PCI Express testing o...view moreThis document primarily covers PCI Express testing of root complexes, switches, bridges, and endpoints for the standard configuration mechanisms, registers, and features in Chapter 7 of the PCI Express Base Specification, Revision 2.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.
show less
This document primarily covers PCI Express testing o...view moreThis document primarily covers PCI Express testing of root complexes, switches, bridges, and endpoints for the standard configuration mechanisms, registers, and features in Chapter 7 of the PCI Express Base Specification, Revision 2.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.
show less
This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building add-in cards or system boards to the PCI Express Card Electromechanical Specification, Revision 2.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.
show less
This test specification primarily covers testing of ...view moreThis test specification primarily covers testing of all PCI Express Port types for compliance with the link layer requirements in Chapter 3 of the PCI Express Base Specification. At this point, this specification does not describe the full set of PCI Express tests for all link layer requirements. Going forward, as the testing gets mature, it is expected that more tests may be added as deemed necessary.
show less
This is a companion specification to the PCI Express...view moreThis is a companion specification to the PCI Express Base Specification. Its primary focus is the implementation of cabled PCI Express®. The discussions are confined to copper cabling and their connector requirements to meet the PCI Express signaling needs at 5.0 GT/s. No assumptions are made regarding the implementation of PCI Express compliant Subsystems on either side of the cabled Link; e.g., PCI Express Card Electromechanical (CEM), ExpressCard5 ™, ExpressModule™, PXI Express™, system board, or any other form factor. Such form factors are covered in other separate specifications.
show less
This is a companion specification to the PCI Express...view moreThis is a companion specification to the PCI Express Base Specification. Its primary focus is the implementation of cabled PCI Express®. The discussions are confined to copper cabling and their connector requirements to meet the PCI Express signaling needs at 5.0 GT/s. No assumptions are made regarding the implementation of PCI Express compliant Subsystems on either side of the cabled Link; e.g., PCI Express Card Electromechanical (CEM), ExpressCard5 ™, ExpressModule™, PXI Express™, system board, or any other form factor. Such form factors are covered in other separate specifications.
show less
This specification defines an implementation for sma...view moreThis specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 2.0. Where this specification does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs.
show less
This specification defines an implementation for sma...view moreThis specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 2.0. Where this specification does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs.
show less
This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI™, PCI-X, and PCI Express® systems in a host computer.
show less
This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
show less
This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
show less
The purpose of this document is to specify PCI™ I/O ...view moreThe purpose of this document is to specify PCI™ I/O virtualization and sharing technology. The specification is focused on single root topologies; e.g., a single computer that supports virtualization technology.
show less
The purpose of this document is to specify PCI™ I/O ...view moreThe purpose of this document is to specify PCI™ I/O virtualization and sharing technology. The specification is focused on single root topologies; e.g., a single computer that supports virtualization technology.
show less
This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
show less
This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
show less
This specification describes the extensions required...view moreThis specification describes the extensions required to allow PCI Express Devices to interact with an address translation agent (TA) in or above a Root Complex (RC) to enable translations of DMA addresses to be cached in the Device. The purpose of having an Address Translation Cache (ATC) in a Device is to minimize latency and to provide a scalable distributed caching solution that will improve I/O performance while alleviating TA resource pressure. This specification must be used in conjunction with the PCI Express Base Specification, Revision 1.1, and associated ECNs.
show less
This document primarily covers PCI Express testing o...view moreThis document primarily covers PCI Express testing of root complexes, switches, bridges, and endpoints for the standard configuration mechanisms, registers, and features in Chapter 7 of the PCI Express Base Specification, Revision 2.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.
show less
This document contains a list of Test Assertions and...view moreThis document contains a list of Test Assertions and a set of Test Definitions pertaining to the Transaction Layer. Assertions are statements of spec requirements which are measured by the algorithm details as specified in the Test Definitions. “Basic Functional Tests” are Test Algorithms which perform basic tests for key elements of Transaction Layer device functionality. This document does not describe a full set of PCI Express tests and assertions and is in no way intended to measure products for full design validation. Tests described here should be viewed as tools to checkpoint the result of product validation – not as a replacement for that effort.
show less
The purpose of this document is to specify PCI® I/O ...view moreThe purpose of this document is to specify PCI® I/O virtualization and sharing technology. The specification is focused on multi-root topologies; e.g., a server blade enclosure that uses a PCI Express® Switch-based topology to connect server blades to PCI Express Devices or PCI Express to-PCI Bridges and enable the leaf Devices to be serially or simultaneously shared by one or more System Images (SI). Unlike the Single Root IOV environment, independent SI may execute on disparate processing components such as independent server blades.
show less
The main objective of this specification is to suppo...view moreThe main objective of this specification is to support PCI Express® add-in cards that require higher power than specified in the PCI Express Card Electromechanical Specification and the PCI Express x16 Graphics 150W-ATX Specification.
show less
This specification defines an implementation for sma...view moreThis specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 1.1. Where this specification does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs.
show less
This specification defines an implementation for sma...view moreThis specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 1.1. Where this specification does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs.
show less
The purpose of this document is to specify PCI™ I/O ...view moreThe purpose of this document is to specify PCI™ I/O virtualization and sharing technology. The specification is focused on single root topologies; e.g., a single computer that supports virtualization technology.
show less
This specification is a companion for the PCI Expres...view moreThis specification is a companion for the PCI Express Base Specification, Revision 2.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express® Mini Card are covered in other separate specifications.
show less
This specification is a companion for the PCI Expres...view moreThis specification is a companion for the PCI Express Base Specification, Revision 2.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express® Mini Card are covered in other separate specifications.
show less
This specification describes the extensions required...view moreThis specification describes the extensions required to allow PCI Express Devices to interact with an address translation agent (TA) in or above a Root Complex (RC) to enable translations of DMA addresses to be cached in the Device. The purpose of having an Address Translation Cache (ATC) in a Device is to minimize latency and to provide a scalable distributed caching solution that will improve I/O performance while alleviating TA resource pressure. This specification must be used in conjunction with the PCI Express Base Specification, Revision 1.1, and associated ECNs.
show less
This is a companion specification to the PCI Express...view moreThis is a companion specification to the PCI Express Base Specification. Its primary focus is the implementation of cabled PCI Express®. The discussions are confined to copper cabling and their connector requirements to meet the PCI Express signaling needs at 2.5 GT/s. No assumptions are made regarding the implementation of PCI Express compliant Subsystems on either side of the cabled Link; e.g., PCI Express Card Electromechanical (CEM), ExpressCard™, ExpressModule™, PXI Express™, system board, or any other form factor. Such form factors are covered in other separate specifications.
show less
This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
show less
This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.
show less
This specification is a companion for the PCI Expres...view moreThis specification is a companion for the PCI Express Base Specification, Revision 1.1. Its primary focus is the implementation of an evolutionary strategy with the current PCI desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express Mini Card are covered in other separate specifications.
show less
This specification is a companion for the PCI Expres...view moreThis specification is a companion for the PCI Express Base Specification, Revision 1.1. Its primary focus is the implementation of an evolutionary strategy with the current PCI desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express Mini Card are covered in other separate specifications.
show less
This specification describes the PCI Express archite...view moreThis specification describes the PCI Express architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express specification.
show less
This specification describes the PCI Express archite...view moreThis specification describes the PCI Express architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express specification.
show less
This document is a companion specification to the PC...view moreThis document is a companion specification to the PCI Express Base Specification. Its primary focus is the implementation of a modular I/O form factor that is focused on the needs of workstations and servers from mechanicals and electrical requirements. The discussions are confined to the modules and their chassis slots requirements. Other form factors are covered in other separate specifications.
show less
The objectives of this specification are Support for...view moreThe objectives of this specification are Support for PCI Express™ graphics add-in cards that are higher power than specified in the PCI Express Card Electromechanical Specification, Forward looking for future scalability, Allow evolution of the PC architecture including graphics, Upgradeability, and Enhanced end user experience.
show less
This addendum to the PCI Express Base 1.0a describes...view moreThis addendum to the PCI Express Base 1.0a describes a low power extension intended primarily to support the reduced power requirements of mobile platforms. Its scope is restricted to the electrical layer and corresponds to Section 4.3 of PCI Express Base 1.0a.
show less
...view more
This specification describes the PCI Express to PCI/PCI-X bridge (also referred to herein as PCI Express bridge) architecture, interface requirements, and the programming model.
show less
This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.
show less
This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.
show less
This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.
show less
This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI™, PCI-X, and PCI Express® systems in a host computer.
show less
This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.
show less
This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.
show less
This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.
show less
This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.
show less
This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI™, PCI-X, and PCI Express® systems in a host computer.
show less
This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.
show less
The goal of this specification is to establish a sta...view moreThe goal of this specification is to establish a standard set of PCI peripheral power management hardware interfaces and behavioral policies. Once established, this infrastructure enables an operating system to intelligently manage the power of PCI functions and buses.
show less
...view more
This document contains the formal specifications of the protocol, electrical, and mechanical features of the PCI Local Bus Specification, Revision 3.0, as the production version effective February 3, 2004. The PCI Local Bus Specification, Revision 2.3, issued March 29, 2002, is not superseded by this specification.
show less
This document contains the formal specifications of ...view moreThis document contains the formal specifications of the protocol, electrical, and mechanical features of the PCI Local Bus Specification, Revision 3.0, as the production version effective February 3, 2004. The PCI Local Bus Specification, Revision 2.3, issued March 29, 2002, is not superseded by this specification.
show less
This specification defines the behavior of a complia...view moreThis specification defines the behavior of a compliant PCI-to-PCI bridge. A PCI-to-PCI bridge that conforms to this specification and the PCI Local Bus Specification is a compliant implementation. Compliant bridges may differ from each other in performance and, to some extent, functionality.
show less
This specification defines the behavior of a complia...view moreThis specification defines the behavior of a compliant PCI-to-PCI bridge. A PCI-to-PCI bridge that conforms to this specification and the PCI Local Bus Specification is a compliant implementation. Compliant bridges may differ from each other in performance and, to some extent, functionality.
show less
This document contains the formal specifications of ...view moreThis document contains the formal specifications of the protocol, electrical, and mechanical features of the PCI Local Bus Specification, Revision 2.3, as the production version effective March 29, 2002. The PCI Local Bus Specification, Revision 2.2, issued December 18, 1998, is superseded by this specification.
show less
...view more
The primary objective of this specification is to enable higher availability of file and application servers by standardizing key aspects of the process of removing and installing PCI add-in cards while the system is running. Although these same principles can be applied to desktop and portable systems using PCI buses, the operations described here target server platforms.
show less
The primary purpose of this document is to specify a...view moreThe primary purpose of this document is to specify a standard implementation of a PCI Hot-Plug Controller called the Standard Hot-Plug Controller (SHPC).
show less
...view more
The Mini PCI Specification defines an alternate implementation for small form factor PCI cards referred to in this specification as a Mini PCI Card. This specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Local Bus Specification.
show less
This document describes the software interface prese...view moreThis document describes the software interface presented by the PCI BIOS functions. This interface provides a hardware independent method of managing PCI devices in a host computer.
show less
