The PCIe 6.0 specification introduces PAM4 (Pulse Amplitude Modulation with 4 levels) signaling, low-latency Forward Error Correction (FEC) and Flit (Flow Control Unit)-based encoding.

The general timeline is 12-18 months after the release of the final specification.

Yes, Flit Mode supports an optional error injection mechanism.

The PCIe 6.0 specification supports a data rate of 64 GT/s and up to 256 GB/s via a x16 configuration, while providing low latency, minimal complexity and reduced bandwidth overhead. PCIe 6.0 technology delivers a doubling of the 32 GT/s and 128 GB/s bit rate of the PCIe 5.0 specification.

The final specification is available to all PCI-SIG members; join PCI-SIG to receive a copy. Members can download the specification here. 

PCIe 6.0 technology is cost-effective and scalable. By adopting PCIe 6.0 technology in their roadmaps, companies can future-proof their products and offer customers the high bandwidth and low latency technology they need.

Yes, automatic translation occurs at the boundaries

The initial target applications of PCIe 6.0 technology include servers, AI/ML, networking and storage in data-intensive markets like data center, HPC, industrial, automotive and Military/Aerospace.

Lightweight Forward Error Correction (FEC) and strong Cyclic Redundancy Check (CRC) are the two primary methods used in the PCIe 6.0 specification to correct errors. With the 64 GT/s data rate enabled by PAM4 encoding in the PCIe 6.0 specification, the bit error rate (BER) was several orders of magnitude higher than the 10-12 BER in all prior generations. FEC and CRC mitigate the bit error rate and allow the PCIe 6.0 specification to reach new levels of performance. Flit Mode supports the higher BER expected in PAM4 (10^-6 vs 10^-12 in NRZ). This can provide increased resilience in NRZ environments.

Yes, for each revision of the base specification, PCI-SIG develops compliance tests and related collateral consistent with the requirements of the new architecture. All of these compliance requirements are incremental in nature and build on the prior generation of the architecture. PCI-SIG anticipates releasing compliance specifications as they mature along with corresponding tests and measurement criteria. PCIe 6.0 Preliminary FYI testing is anticipated to begin in 2023.

Heterogeneous computing applications like artificial intelligence, machine learning and deep learning require a high-performance, low-latency I/O interconnect with additional performance over PCIe 5.0.

Flit (Flow Control Unit) mode is the unit of data exchange in the PCIe 6.0 specification. PCI-SIG adopted a 256-Byte Flit structure, which includes the variable-sized Transaction  Layer Packets (TLPs) and Data Link Layer Payloads (DLLPs). This is a necessary change due to the move to PAM4 encoding and Forward Error Correction (FEC), which only works on fixed-size data packets. Flit Mode is required for 64 GT/s PAM4 and is supported at all Link speeds. Once a Link trains to Flit Mode, it will stay in Flit Mode as long as that Link remains LinkUp.

The forthcoming PCIe 7.0 specification is planned for 2025.  

PCIe 7.0 technology will expand the PCI-SIG roadmap to include data-intensive applications and markets, including 800 Gig Ethernet, Artificial Intelligence and Machine Learning (AI/ML), High Performance Computing (HPC), Quantum Computing, Hyperscale Data Centers and Cloud.

The PCI-SIG has recently accepted this technology as a contribution from its members and will soon announce a suitable name for it.

This adaptation of the PCIe architecture requires no new software. It reuses the existing, ubiquitous support in all major Operating Systems (e.g. pci.sys bus driver on Windows platforms). This includes existing support for device discovery, configuration and control.

As PCs become lighter and thinner and tablets and smartphones become more functional, consumers want seamless, always on/always connected functionality from their computing devices. To respond to these market expectations, device manufacturers need efficient, intelligent I/O technologies. The PCIe architecture satisfies all of these requirements, and with the adaptation to operate over the M-PHY specification it can deliver consistent high performance in power-constrained platforms such as ULT laptops, tablets and smartphones. By delivering this technology, the PCI-SIG is meeting the emerging needs of its members and the industry.

The initial application of this technology is anticipated to be high-performance wireless communications with other applications based on device design requirements. Future implementations are expected in the handheld device market, including smartphones, tablets and other ultra-low power applications. As a power-efficient, general-purpose load-store I/O architecture, component and device designers can implement this technology in other I/O expansion usage models of their choosing as well.

This collaboration will enable component and device manufacturers to take advantage of the reduction in I/O technology proliferation, allowing them to reduce their product development time, product validation time and significantly increase their time to market. The mobile and handset industry can realize these benefits today by adopting PCIe architecture adapted to run over M-PHY.