As with prior generations, PCIe 5.0 adds some new optional capabilities and features. These include:

• Alternate protocol support – This feature allows non-PCIe protocols to be based on the high-performance and robust PCIe PHY layer. This allows such protocols to be developed much more quickly.
• Bypass Link equalization options – Two equalization bypass options are added: No Equalization Needed, and Equalization Bypass to Highest Data Rate. These bypass options can be used to reduce the time needed to bring up a PCIe Link to its highest data rate at start-of-day.
• Precoding – Added to avoid LCRC/CRC aliasing for cases where a received clock-like bit pattern can lead to contiguous burst errors.
• Component Measurement and Authentication (CMA) – Added to PCIe 5.0 by way of an Engineering Change Notice (ECN), CMA provides the mechanisms to perform security exchanges with a component or a Device Function. This capability, for example, provides the means to establish the hardware and firmware identities of a Function before assigning it to a Virtual Machine.   
• Integrity and Data Encryption (IDE) – Added to PCIe 5.0 by way of an ECN, this capability provides confidentiality and integrity protection for communications between two Ports connected through one or more PCIe Links.

For certain Decision Feedback Equalizer (DFE) settings, certain received bit patterns, such as clock patterns, can cause contiguous burst errors, which in turn can cause LCRC/CRC aliasing. Precoding involves XORing the current bit with the previous bit. That has the effect of converting long contiguous burst errors into two random bit flips that can be reliably detected by CRC. PCIe 5.0 adds the ability for Link partners to request precoding at data rates where one partner or the other requires it.

PCI-SIG is proud of its long heritage of developing compatible architectures and its members have consistently produced compatible and interoperable products. In keeping with this tradition, the PCIe 5.0 architecture is compatible with prior generations of this technology, from software to clocking architecture to mechanical interfaces. PCIe 1.x, 2.x, 3.x, and 4.x cards will seamlessly plug into PCIe 5.0-capable slots and operate at the highest performance levels possible. Similarly, all PCIe 5.0 cards will plug into PCIe 1.x-, PCIe 2.x-, PCIe 3.x- and PCIe 4.x-capable slots and operate at the highest performance levels supported by those configurations.

The PCIe 5.0 specification addresses the many applications pushing for increased bandwidth at a low cost, including server, workstation, desktop PC, notebook PC, tablets, embedded systems, peripheral devices, high-performance computing markets, and more. The target implementations are entirely at the discretion of the designer.

PCI-SIG attempts to define and evolve the PCIe architecture in a manner consistent with low-cost and high-volume manufacturability considerations. While PCI-SIG cannot comment on design choices and implementation costs, optimized silicon, die size, and power consumption continue to be important considerations that inform PCIe specification development and architecture evolution.

For each new PCIe generation, PCI-SIG develops compliance tests and the related collateral consistent with the requirements of the new architecture. All these compliance requirements are incremental in nature and build upon the prior generation of the architecture. PCI-SIG releases compliance specifications as they mature along with corresponding tests and measurement criteria. Each revision of the PCIe technology maintains its own criteria for product interoperability and admission into the PCI-SIG integrators List.

Official Compliance Testing for PCIe 5.0 has been available since April 2022 and many PCIe 5.0 compliant systems, components, and add-in cards have already been added to the Integrators List.

Retimers were introduced with PCIe 4.0. Up to two Retimers are allowed between the Upstream Port and the Downstream Port of a Link. They are used when necessary to reliably extend the achievable channel length between two PCIe Ports. PCIe 4.0 and PCIe 5.0 Retimers are Physical Layer protocol aware. That is, they participate in Link Equalization, and they adjust their data rate of operation and their Link width in concert with the Upstream and Downstream Ports of the Link.

Heterogeneous computing applications like artificial intelligence, machine learning and deep learning require a high-performance, low-latency I/O interconnect with additional performance over PCIe 5.0.

The initial target applications of PCIe 6.0 technology include servers, AI/ML, networking and storage in data-intensive markets like data center, HPC, industrial, automotive and Military/Aerospace.

The PCIe 6.0 specification supports a data rate of 64 GT/s and up to 256 GB/s via a x16 configuration, while providing low latency, minimal complexity and reduced bandwidth overhead. PCIe 6.0 technology delivers a doubling of the 32 GT/s and 128 GB/s bit rate of the PCIe 5.0 specification.

The PCIe 6.0 specification introduces PAM4 (Pulse Amplitude Modulation with 4 levels) signaling, low-latency Forward Error Correction (FEC) and Flit (Flow Control Unit)-based encoding.

Yes, PCIe 6.0 products will interoperate and maintain backwards compatibility with all previous generations of PCI Express technology.

Yes, for each revision of the base specification, PCI-SIG develops compliance tests and related collateral consistent with the requirements of the new architecture. All of these compliance requirements are incremental in nature and build on the prior generation of the architecture. PCI-SIG anticipates releasing compliance specifications as they mature along with corresponding tests and measurement criteria. PCIe 6.0 Preliminary FYI testing is anticipated to begin in 2023.

PCIe 6.0 technology is cost-effective and scalable. By adopting PCIe 6.0 technology in their roadmaps, companies can future-proof their products and offer customers the high bandwidth and low latency technology they need.

The general timeline is 12-18 months after the release of the final specification.

PAM4 (Pulse Amplitude Modulation with 4 Levels) is a multilevel signal modulation format used to transmit data. NRZ uses two levels of signaling, while PAM4 uses four levels. It packs two bits of information into the same amount of time on a serial channel.  The utilization of PAM4 allows the PCIe 6.0 specification to reach 64 GT/s data rate and up to 256 GB/s bidirectional bandwidth via a x16 configuration.

Flit (Flow Control Unit) mode is the unit of data exchange in the PCIe 6.0 specification. PCI-SIG adopted a 256-Byte Flit structure, which includes the variable-sized Transaction  Layer Packets (TLPs) and Data Link Layer Payloads (DLLPs). This is a necessary change due to the move to PAM4 encoding and Forward Error Correction (FEC), which only works on fixed-size data packets. Flit Mode is required for 64 GT/s PAM4 and is supported at all Link speeds. Once a Link trains to Flit Mode, it will stay in Flit Mode as long as that Link remains LinkUp.

Yes, automatic translation occurs at the boundaries

Yes, Flit Mode supports an optional error injection mechanism.

A great deal of care has been taken to avoid significant impacts to existing software, but some changes could not be avoided in order to take full advantage of Flit mode. Here are some examples:

• The new TLP format changes how we interpret error logs
• Inter-hierarchy (a.k.a., inter-segment) routing allows the use of larger trees of PCIe technology devices to directly communicate
• Defined routing behavior for all TLP-type codes allows for additional TLPs to be defined without needing to change switches

Bit tags were increased to 14 bits to support a larger number of outstanding non-posted requests. We anticipate this wider size to work for at least the next generation as well.

Lightweight Forward Error Correction (FEC) and strong Cyclic Redundancy Check (CRC) are the two primary methods used in the PCIe 6.0 specification to correct errors. With the 64 GT/s data rate enabled by PAM4 encoding in the PCIe 6.0 specification, the bit error rate (BER) was several orders of magnitude higher than the 10-12 BER in all prior generations. FEC and CRC mitigate the bit error rate and allow the PCIe 6.0 specification to reach new levels of performance. Flit Mode supports the higher BER expected in PAM4 (10^-6 vs 10^-12 in NRZ). This can provide increased resilience in NRZ environments.

The PCIe 7.0 specification is targeted to double the data rate of the PCIe 6.0 specification (64 GT/s) to 128 GT/s.

PCI-SIG technical workgroups will be developing the PCIe 7.0 specification with the following feature goals:

• Delivering 128 GT/s raw bit rate and up to 512 GB/s bi-directionally via x16 configuration
• Utilizing PAM4 (Pulse Amplitude Modulation with 4 levels) signaling
• Focusing on the channel parameters and reach
• Continuing to deliver the low-latency and high-reliability targets
• Improving power efficiency
• Maintaining backwards compatibility with all previous generations of PCIe technology

The PCI-SIG has recently accepted this technology as a contribution from its members and will soon announce a suitable name for it.

As a broadly adopted technology standard, PCIe benefits from several decades of innovations with universal support in all major Operating Systems, a robust device discovery and configuration mechanism, and comprehensive power management capabilities that very few, if any, of the other I/O technologies can match. PCIe technology has a flexible, layered protocol that enables innovations to occur at each layer of the architecture independent of the other layers. In this way, power-efficient PHY technologies, such as MIPI M-PHY, can be integrated with the familiar and highly functional PCIe protocol stack to deliver best-in-class and highly scalable I/O performance in tablet and smartphone devices.

This collaboration will enable component and device manufacturers to take advantage of the reduction in I/O technology proliferation, allowing them to reduce their product development time, product validation time and significantly increase their time to market. The mobile and handset industry can realize these benefits today by adopting PCIe architecture adapted to run over M-PHY.

The initial application of this technology is anticipated to be high-performance wireless communications with other applications based on device design requirements. Future implementations are expected in the handheld device market, including smartphones, tablets and other ultra-low power applications. As a power-efficient, general-purpose load-store I/O architecture, component and device designers can implement this technology in other I/O expansion usage models of their choosing as well.

This adaptation of the PCIe architecture requires no new software. It reuses the existing, ubiquitous support in all major Operating Systems (e.g. pci.sys bus driver on Windows platforms). This includes existing support for device discovery, configuration and control.