First, developers must use silicon that has passed the PCI-SIG compliance program. PCI Express components that successfully pass the PCI-SIG compliance tests may be useable in an ExpressCard module if they allow for a module design which meets the additional requirements (e.g., power management, power and thermal) detailed in the ExpressCard standard.

The PCIe 1.1 specification was developed to meet the needs of most I/O platforms. However a few applications, such as graphics, continue to require more bandwidth in order to enrich user experiences. PCI-SIG also saw the opportunity to add new functional enhancements (listed below), as well as incorporate all edits it had received to the PCIe 1.1 spec (via ECNs). In response to these needs, PCI-SIG developed PCI Express 2.0 (PCIe 2.0). It provides faster signaling, which doubles the bit rate from 2.5GT/s to 5GT/s.

While doubling the bit rate satisfies high-bandwidth applications, faster signaling has the advantage of allowing various interconnect links to save cost by adopting a narrow configuration. For example, a PCI Express 1.1 x8 link (8 lanes) yields a total aggregate bandwidth of 4Gbps, which is the same bandwidth obtained from a PCI Express 2.0 x4 link (4 lanes) that adopts the 5GT/s signaling technology. This can result in significant savings in platform implementation cost while achieving the same performance level. Backward compatibility is retained as 2.5 GT/s adapters can plug into 5.0 GT/s slots and will run at the slower rate. Conversely, PCIe 2.0 adapters running at 5.0 GT/s can plug into existing PCIe slots and run at the slower rate of 2.5 GT/s.

The PCIe Base 2.0 specification supports both 2.5GT/s and 5GT/s signaling rates, in order to retain backward compatibility with existing PCIe 1.0 and 1.1 systems. Aside from the faster bit rate, there are a number of improvements in this specification that allow greater flexibility and reliability in designing PCIe links. For example, the interconnect can be dynamically managed for platform power and performance considerations through software controls. Another significant RAS feature is the inclusion of new controls to allow a PCIe link to continue to function even when some lanes become non-operational.

Yes. The PCIe Base 2.0 specification supports both the 2.5GT/s and 5GT/s signaling technologies. A device designed to the PCIe Base 2.0 specification may support 2.5GT/s, 5GT/s or both. However, a device designed to operate specifically at 5GT/s must also support 2.5GT/s signaling. The PCIe Base specification covers chip-to-chip topologies on the system board. For I/O extensibility across PCIe connectors, the Card Electromechanical (CEM) and ExpressModule? specifications will also need to be updated, but this work will not impact mechanical compatibility of the slots, cards or modules.

The most predominant feature in PCIe 2.0 is 5GT/s speed, which includes new mechanisms for software control of link speed, reporting of speed and width changes, and control of loopback. Other new features include:

• PCI compatibility using the established PCI software programming models, thus facilitating a smooth transition to new hardware while allowing software to evolve to take advantage of PCI Express features
• Enhanced Completion Timeout Control, which includes required and optional aspects, reduces false timeouts and increases the ability to 'tune' the timeouts
• Function Level Reset and Access Control Services, giving enhanced robustness and support of certain IOV features (optional)
• Slot Power Limit Changes to allow for higher powered slots, which support the newer, high-performance graphics cards; this new feature works in tandem with the 300W Card Electro-mechanical specification
• Speed Signaling Controls to enable software to determine whether a device can operate at a specific signaling rate, which can be used to reduce power consumption, as well as provide gross level I/O to memory

The same set of core applications, high-performance graphics, enterprise-class storage and high-speed networking that benefited from the introduction of PCIe 1.0 architecture have led the charge for adoption of PCIe 2.0.

The established PCIe ecosystem delivers both pre-silicon and post-silicon tools to assist design engineers with implementing PCIe 2.0 products. In addition, PCI-SIG provides updated hardware test fixtures and test software upgrades to facilitate compliance verification at its Compliance Workshops.

PCI-SIG is the sole source for PCIe specifications. In addition, both the PCI-SIG and its members provide a plethora of technical and marketing collateral in support of the PCIe architecture. Please visit www.pcisig.com for additional information.

Link Upconfigure means the device is capable of increasing the link width. When Upconfigure is supported by both devices on a link, the link width may be reduced to conserve power. When link use is going to increase, the devices will increase the link width to support the needed high data rate preferred by the device.

The purpose of the "inferred" electrical idle is to permit a method of detecting an electrical idle that does not use an analog circuit. Using an analog circuit can be difficult at 5.0 GT/s and the inferred method is an alternate (permitted) method.

The Loopback slave transitions to Loopback.Active immediately after exiting Electrical Idle following the link speed change. It attempts to acquire symbol lock on all of the lanes that were active when it entered Loopback.Entry.

Endpoints that do not support Address Translation Services set the AT field to 00b on transmitted TLPs and ignore the AT field on received TLPs.

Configuration softrware reads configuration space address 00h (using different bus, device and function numbers). When it gets a response, it knows a device exists at that ID.

Transition to Recovery.Idle after sending the 16 TS2s since the requirements for that transition are met.

The Endpoint is required to send an Ack for the PME_Turn_Off message. There is no valid reason for an extended delay of the Ack.

The intent is for this error case to be handled as a Poisoned TLP Received error. Errata is being developed against the 2.1 Base spec to clarify this. Due to ambiguous language in earlier versions of the spec, a component will be permitted to handle this error as an Unsupported Request, but this will be strongly discouraged.

Yes, when a link reports DL_Down the upsteam port on the switch (and all other downstream devices) are reset.

The section 2.9.1 text covers two contexts. The context of a Downstream Port in DL_Down and the context of an Upstream Port in DL_Down. Care must be taken to apply the requirements in this section to the correct context.

The slave stays in Loopback.Active indefinitely until it receives an EIOS (or detects or infers an Electrical Idle). There is not timeout.

It means the next state is Detect.Active after a 12 ms timeout, or the next state is Detect.Active (prior to the end of the 12 ms timer) if Electrical Idle is broken on any Lane.

If a Switch supports the LTR feature, it must support the feature on its Upstream Port and all Downstream Ports.

The received Link number must match the transmitted Link number. The received Lane number must match the transmitted Lane number. The received data rate identifier must be the same on all received lanes (but is not required to be the same as the transmitted data rate identifier). The received Link Upconfigure Capability bit must be the same on all received lanes (but is not required to be the same as the transmitted Link Upconfigure Capability bit).

When software sets the Secondary Bus Reset bit in a Switch Downstream Port, the Downstream Port must not reset any of its own configuration settings, and it must transition the Link below it to the Hot Reset state, assuming the Link is not down. The description of the Secondary Bus Reset bit in Section 7.5.3.6 states "Port configuration registers must not be changed, except as required to update Port status."

Appropriate disparity means that the D symbol must have the correct disparity for the specified sequence of symbols.

Yes (up to a total of 5 bits). Also to avoid confusion for the function, software sets each of the low order message data bits to 0, that correspond to the low order message data bits the function is permitted to modify to generate its system software allocated vectors.

For this case, the LTSSM of the Downstream Port above the Endpoint is already in the Hot Reset state, since that is how it transmitted TS1 Ordered Sets with the Hot Reset bit asserted.

The reference in the spec should be to Section 5.3.2.1, which provides more detail (note that this reference will be fixed through upcoming errata to the 2.1 spec).

For the first case, the Endpoint must handle the Request as an Unsupported Request. For the second case, it is recommended that the Endpoint handle the Request as a Malformed TLP, but the Endpoint is permitted to handle the Request as an Unsupported Request.

It should be handled as an unsupported request.

The active lanes must be consecutively numbered lanes starting with lane 0. Your example would configure as a x1 link.

All PCI Express device Functions (including root ports) that are capable of generating interrupts must implement MSI or MSI-X or both.

The transition to Polling.Configuration follows either 8 consecutive TS1s, or 8 consecutive TS2s on all lanes that detected a receiver in Detect. Note that the intent of the spec also is to allow the 8 to be any mixture of 8 consecutive TS1s or TS2s for this particular case (not necessarily for other LTSSM transitions, however). Note also that the PCIe 2.0 Errata item A42 (Polling.Active Substate) modifies this section (see Errata item A42 at www.pcisig.com/specifications/pciexpress/base2/).

It is recommended that only the highest precedence error associated with a single TLP be reported. However, it is recognized that reasonable implementations may not be able to support the recommended precedence order, which is why this is recommended rather than required behavior.

A device that supports 5GT/s must also be able to support and operate at 2.5GT/s.

PCIe Link is symmetric - so each component has the same number of Transmitters as Receivers. Since device B has transmitters on only 4 lanes, it also has receivers on 4 Lanes. Hence it would not be capable of detecting receivers on 8 lanes of device A.

Since device B has transmitters on only 4 lanes, it cannot transmit TS1s on more than 4 lanes. Device A will transmit TS1s on only the lanes where it detected receivers (and that is a maximum of 4 lanes).

The bit rate for PCIe 3.0 is 8GT/s. This bit rate represents the most optimum tradeoff between manufacturability, cost, power and compatibility.
The PCI-SIG analysis covered multiple topologies and configurations, including servers. All of these studies confirmed the feasibility of 8GT/s signaling with low-cost enablers and with minimal increases in power, silicon die size and complexity.

The PCIe 2.0 bit rate is specified at 5GT/s, but with the 20 percent performance overhead of the 8b/10b encoding scheme, the delivered bandwidth is actually 4Gbps. PCIe 3.0 removes the requirement for 8b/10b encoding and uses a more efficient 128b/130b encoding scheme instead. By removing this overhead, the interconnect bandwidth can be doubled to 8Gbps with the implementation of the PCIe 3.0 specification. This bandwidth is the same as an interconnect running at 10GT/s with the 8b/10b encoding overhead. In this way, the PCIe 3.0 specifications deliver the same effective bandwidth, but without the prohibitive penalties associated with 10GT/s signaling, such as PHY design complexity and increased silicon die size and power. The following table summarizes the bit rate and approximate bandwidths for the various generations of the PCIe architecture: PCIe architecture Raw bit rate Interconnect bandwidth Bandwidth per lane per direction Total bandwidth for x16 link
PCIe 1.x 2.5GT/s 2Gbps ~250MB/s ~8GB/s
PCIe 2.x 5.0GT/s 4Gbps ~500MB/s ~16GB/s
PCIe 3.0 8.0GT/s 8Gbps ~1GB/s ~32GB/s

Total bandwidth represents the aggregate interconnect bandwidth in both directions.

The PCIe 3.0 specifications comprise the Base and the Card Electro-mechanical (CEM) specifications. There may be updates to other form factor specifications as the need arises. Within the Base specification, which defines a chip-to-chip interface, updates have been made to the electrical section to comprehend 8GT/s signaling. As the technology definition progresses through PCI-SIG specification development process, additional ECN and errata will be incorporated with each review cycle. For example, the current PCIe protocol extensions that address interconnect latency and other platform resource usage considerations have been rolled into the PCIe 3.0 specification revisions. The final PCIe 3.0 specification consolidates all ECN and errata published since the release of the PCIe 2.1 specification, as well as interim errata.

PCI-SIG is proud of its long heritage of developing compatible architectures and its members have consistently produced compatible and interoperable products. In keeping with this tradition, the PCIe 3.0 architecture is fully compatible with prior generations of this technology, from software to clocking architecture to mechanical interfaces. That is to say PCIe 1.x and 2.x cards will seamlessly plug into PCIe 3.0-capable slots and operate at their highest performance levels. Similarly, all PCIe 3.0 cards will plug into PCIe 1.x- and PCIe 2.x-capable slots and operate at the highest performance levels supported by those configurations.

The following chart summarizes the interoperability between various generations of PCIe and the resultant interconnect performance level:
   

In short, the notion of the compatible highest performance level is modeled after the mathematical least common denominator (LCD) concept. Also, PCIe 3.0 products will need to support 8b/10b encoding when operating in a pre-PCIe 3.0 environment.

The PCIe protocol extensions are primarily intended to improve interconnect latency, power and platform efficiency. These protocol extensions pave the way for better access to platform resources by various compute- and I/O-intensive applications as they interact with and through the PCIe interconnect hierarchy. There are multiple protocol extensions and enhancements being developed and they range in scope from data reuse hints, atomic operations, dynamic power adjustment mechanisms, loose transaction ordering, I/O page faults, BAR resizing and so on. Together, these protocol extensions will increase PCIe deployment leadership in emerging and future platform I/O usage models by enabling significant platform efficiencies and performance advantages.

PCI-SIG released the PCIe 3.0 specification on November 17, 2010.

8b/10b encoding is a byte-oriented coding scheme that maps each byte of data into a 10-bit symbol. It guarantees a deterministic DC wander and a minimum edge density over a per-bit time continuum. These two characteristics permit AC coupling and a relaxed clock data recovery implementation. Since each byte of data is encoded as a 10-bit quantity, this encoding scheme guarantees that in a multi-lane system, there are no bubbles introduced in the lane striping process.

Scrambling is a technique where a known binary polynomial is applied to a data stream in a feedback topology. Because the scrambling polynomial is known, the data can be recovered by running it through a feedback topology using the inverse polynomial. Scrambling affects the PCIe architecture at two levels: the PHY layer and the protocol layer immediately above the PHY. At the PHY layer, scrambling introduces more DC wander than an encoding scheme such as 8b/10b; therefore, the Rx circuit must either tolerate the DC wander as margin degradation or implement a DC wander correction capability. Scrambling does not guarantee a transition density over a small number of unit intervals, only over a large number. The Rx clock data recovery circuitry must be designed to remain locked to the relative position of the last data edge in the absence of subsequent edges. At the protocol layer, an encoding scheme such as 8b/10b provides out-of-band control characters that are used to identify the start and end of packets. Without an encoding scheme (i.e. scrambling only) no such characters exist, so an alternative means of delineating the start and end of packets is required. Usually this takes the form of packet length counters in the Tx and Rx and the use of escape sequences. The choice for the scrambling polynomial is currently under study.