Frequently Asked Questions
The following FAQ list was generated using standard responses provided to PCI-SIG members by Technical Support and PCI-SIG Administration. For questions relative to the PCI Specifications, please reference the specifications themselves as the authoritative text.
PCI Express - 3.0
 Section 3.5.2.1 - The M-PCIe ECN contains no information on the REPLAY_TIMER and the Ack Transmission Latency Limit. What are the recommended values for the following?
Gear 1 - Rate A
Gear 1 - Rate B
Gear 2 - Rate A
Gear 2 - Rate B
Gear 3 - Rate A
Gear 3 - Rate B We suggest using the 2.5 GT/s values for Gear 1 and 2 at Rates A and B, and also suggest using the 5.0 GT/s values for Gear 3 at Rates A and B, until clarification is received from the workgroup. This clarification will be included in next errata release. |
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Section 4.2.6.6.1.3 - How can I configure the RC, if permissible, to send 4096 FTS to EP while RC transits out of L0s? Setting the Extended Synch bit in the Link Control register of the two devices on the link will increase the number of FTS Ordered Sets to 4096, but the Extended Synch bit is used only for testing purposes. |
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SECTION 2.2.9 - If a link is up and bus and device numbers are snooped by the Endpoint, then the link is disabled and enabled again, should the Endpoint set the bus and device number fields to zero in a completion that it sends prior to the first CfgWr being received? Yes, when the LTSSM enters the Disabled state, the DLCMSM transitions to DL_Inactive, the Link transitions to DL_Down, and this causes the equivalent of a Hot Reset to the Endpoint. See Sections 2.2.9 & 3.2.1. |
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Section 4.2.6.4.3 - While down configured and a rate change request occurs, do the unused lanes also participate in the rate change? The transmitter of the unused lanes remains in Electrical Idle during the speed change. |
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Has there been a new compliance specification developed for PCIe 3.0? For each revision of its specification, PCI-SIG develops compliance tests and related collateral consistent with the requirements of the new architecture. All of these compliance requirements are incremental in nature and build on the prior generation of the architecture. PCI-SIG anticipates releasing compliance specifications as they mature along with corresponding tests and measurement criteria. Each revision of the PCIe technology maintains its own criteria for product interoperability and admission into the PCI-SIG Integrators List. |
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Section 4.2.6 - Table 4-14 says that Receiver Errors should not be reported in the L0s or L1 states. During L1 entry, an Upstream Port's transmitter may be in Electrical Idle while its receivers are not in Electrical Idle. Similarly, a Port's transmitters may be in Electrical Idle for L0s, while its receivers are not in Electrical Idle. In these situations, should the Port report Receiver Errors such as 8b10b errors? If the receivers are in L0s, Receiver Errors should not be reported. It does not matter whether the transmitters are in L0 or L0s for reporting of Receiver Errors. Section 4.2.6.5 specifies the 3 conditions required for the LTSSM to transition from L0 to L1. Until all of these conditions are satisfied, the LTSSM is in L0 state, and should report Receiver Errors, even if its transmitters are in Electrical Idle. |
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Section 7.8.6 - Is the L1 Exit Latency in the Link Capabilities register only the ASPM L1.0 exit latency or does it include the added ASPM L1.2 to ASPM L1.0 latency? The ASPM L1 Exit Latency in the Link Capabilities register indicates the L1/L1.0 to L0 latency, and does not include added latency due to Clock Power Management, L1.1 or L1.2. |
PCI Express - 4.0
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What are the results of the feasibility testing for the PCIe 4.0 specification? After technical analysis, the PCI-SIG has determined that 16 GT/s on copper, which will double the bandwidth over the PCIe 3.0 specification, is technically feasible at approximately PCIe 3.0 power levels. The preliminary data also confirms that a 16GT/s interconnect can be manufactured in mainstream silicon process technology and can be deployed with existing low-cost materials and infrastructure, while maintaining compatibility with previous generations of PCIe architecture. In addition, the PCI-SIG will investigate advancements in active and idle power optimizations as they become available. |
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What is PCI Express (PCIe) 4.0? What are the requirements for this evolution of the PCIe architecture? PCIe 4.0 is the next evolution of the ubiquitous and general-purpose PCI Express I/O specification. At 16GT/s bit rate, the interconnect performance bandwidth will be doubled over the PCIe 3.0 specification, while preserving compatibility with software and mechanical interfaces. The key requirement for evolving the PCIe architecture is to continue to provide performance scaling consistent with bandwidth demand from a variety of applications with low cost, low power and minimal perturbations at the platform level. One of the main factors in the wide adoption of the PCIe architecture is its sensitivity to high-volume manufacturing capabilities and materials such as FR4 boards, low-cost connectors and so on. |
PCI Express - 5.0
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What bit rates does the PCIe 5.0 specification support and how does it compare to prior PCIe generations? A PCIe Link consists of 1, 2, 4, 8, 12, 16, or 32 Lanes, all operating at one of the supported signaling rates.
A PCIe 5.0 Link consisting of 32 Lanes and operating at a bit rate of 32 GT/s provides an effective raw bandwidth of 128 Gigabytes/second in each direction simultaneously. |
PCI Express - M-PHY
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When and how will the PCI-SIG release the PCIe adaptation layer specification? The PCI-SIG will deliver this technology as an extension to the existing PCIe 3.0 Base specification via ECN by the end of 2012. This technology will be fully integrated into the next release of the PCIe Base specification, PCIe 4.0, enabling ease of access and reference. |