PCI-SIG Developers Conference 2023 Agenda
Day One - Tuesday, June 13, 2022
Track 1 – PCI Express
PCIe 6.0/7.0 Electrical Update
Tuesday, June 13 | 9:30 AM – 10:30 AM PT
Wednesday, June 14 | 9:00 AM – 10:00 AM PT
In this presentation, we will provide an overview of updates to the specification of Reference Clock, Transmitter, Receiver, and Channel Compliance for PCIe 6.0 64 GT/s data rate. We will highlight the key improvements in circuit and channels required for achieving doubling of the data rate over PCIe 5.0.
Speaker: Mohiuddin Mazumder
Mohiuddin Mazumder is a Senior Principal Engineer in Data Center and AI division of Intel. He leads the Electrical Pathfinding and Standards Development work for high-speed differential interconnect technologies. He co-chairs the PCI-SIG Electrical WG and also leads the PCIe 5.0/6.0 Internal and External Cables specification for 32 and 64 GT/s.
PCIe CEM Updates
Tuesday, June 13 | 10:30 AM – 11:30 AM PT
Wednesday, June 14 | 10:30 AM – 11:30 AM PT
This presentation provides updates on the PCI Express CEM specification development work in the PCI-SIG Electromechanical workgroup. The presentation focuses on providing an overview of the changes introduced in PCI Express Card Electromechanical Specification, Rev 5.0 (CEM 5.0) and related ECRs. The presentation also provides an update on the current workgroup direction for CEM 6.0. This includes Add-in Card outline updates, sideband interfaces and connector optimizations.
Speaker: Manisha Nilange
Manisha Nilange is an IO Architect and Analog Engineering Manager at Intel Corp. She has been with Intel Corp for 17 years. She leads multiple form-factor specification development, transmitter and receiver compliance test methodology and compliance tool development. Manisha chairs the CEM, Mini CEM (M.2) and SFF-8639 Connector (U.2) workgroups in PCI-SIG and co-chairs the Serial Enabling workgroup. Manisha holds MS in Electrical Engineering from the University of Texas at Arlington.
PCIe 6.0 PHY Logical
Tuesday, June 13 | 1:00 PM – 2:00 PM PT
Wednesday, June 14 | 11:30 AM – 12:30 PM PT
PCI Express (PCIe) specification has been doubling the data rate every generation in a backwards compatible manner every two to three years. PCIe 6.0 specification has adopted PAM-4 signaling at 64.0 GT/s for maintaining the same channel reach as prior generations. A forward error correction (FEC) mechanism will offset the high BER of PAM-4. A new Flit-based approach with a light-weight, low-latency FEC coupled with a strong CRC and a low-latency link level retry mechanism in PCIe 6.0 specification meets the stringent low-latency, high bandwidth and high reliability goals. Shared credit pooling across multiple virtual channels is included to reduce the area and power overhead while providing the necessary quality of service guarantees. We also present a new low-power state (L0p) that ensures power consumption is proportional to bandwidth usage without impacting the traffic flow.
Speaker: Debendra Das Sharma
Dr. Debendra Das Sharma is an Intel Senior Fellow and a PCI-SIG Board member. He is a leading expert on I/O subsystem and interface architecture. He is a key driver of external standards for PCIe, CXL, and UCIe, and Intel's internal proprietary interfaces, as well as implementation. He holds 150+ US patents and 400+ patents world-wide.
PCIe Compliance: Electrical Deep Dive
Tuesday, June 13 | 2:00 PM – 3:00 PM PT
The PCI-SIG has introduced the 5.0 Integrators List program with a new maximum data rate of 32 GT/s enabling a bi-direction link bandwidth up to 128 GB/s for a x16 link. The PCI Express Architecture PHY Test Specification Rev 5.0 has added 32 GT/s tests to support the faster rate and introduced new testing requirements including uncorrelated jitter and pulse width jitter for all 5.0 Add-in Cards. Discussion of measurement methodologies for Tx Signal Quality and Link Equalization testing will provide insight into the latest measurement methodologies. We will end with a glimpse into 64 GT/s PAM4 Base Spec measurements expected to be introduced for system testing.
Speaker: David Bouse
David Bouse is a Principal Technology Leader at Tektronix with expertise in highspeed SERDES including transmitter and receiver test methodologies, digital signal processing algorithms for NRZ/PAM4 signaling, clock characterization, and automation software architecture.
PCIe 6.0 Protocol Update
Tuesday, June 13 | 3:30 PM – 4:30 PM PT
Wednesday, June 14 | 2:30 AM – 3:30 PM PT
This session covers PCI Express protocol developments over the last year or two, including completed ECNs, selected ECRs under development, and key protocol/spec changes envisioned for PCIe 7.0. Completed ECNs include Relaxed Detect Timing, TDISP, DOE 1.1, Alternative Protocol DLLP Reservation, and Unordered I/O (UIO). Selected ECRs under development include Sideband Signals, CMA-SPDM, 12V2x6 Connector Updates, MMIO Mailbox Passthrough (MMPT), OHC-E Capability Enumeration, Inter-System Bridge (ISB), ATS 2.0, and Remote Memory Operations (RMOps).
Speaker: Joe Cowan
Joe Cowan is a Senior Systems Architect in Hewlett Packard Enterprise. He represents HPE in the PCIe Protocol Workgroup, where he's authored numerous ECNs and errata. During his 44-year career with HP/HPE, Joe has worked in many other areas, including CXL, Gen-Z, InfiniBand, chipset/platform architecture, OS development, and security.
PCIe Strategic Vision Panel Discussion
Tuesday, June 13 | 4:30 PM – 5:30 PM PT
PCIe Compliance: Protocol Deep Dive
Wednesday, June 14 | 1:30 PM – 2:30 PM PT
This presentation discusses the requirements for PCI Express 4.0 and 5.0 Protocol compliance and interoperability. It provides an in-depth review of all Protocol testing performed for the PCIe 4.0 and 5.0 compliance programs—with a focus on requirements for the 5.0 program. Every component of PCIe Protocol compliance is discussed including Link and Transaction Layer, Retimer Logical, Lane Margining, and Configuration testing. This session will also cover the timeline for upcoming Compliance Workshop events worldwide, where members can validate their parts for compliance to the PCI-SIG “Gold” suite of tests.
Speaker: Gordon Getty
Gordon is Technical Marketing Manager at Teledyne LeCroy. He has been working on PCI Express technologies for 22 years. Gordon is an active contributor to the PCI Express Test Specifications. Gordon graduated from Glasgow University with a Bachelor’s degree in Electronics and Music and a MSc in Information Technology from the University of Paisley.
Track 2 – PCI-SIG Architecture
PCI-SIG Architecture Overview
Tuesday, June 13 | 9:30 AM – 10:30 AM PT
This presentation provides an overview of PCI™, PCI-X™ and PCI Express. Basic protocol details, and key concepts such as Configuration Space, Message Signaled Interrupts, Transaction Attributes and Split Transactions which span the spectrum from Conventional PCI through PCI-X to PCI Express are explained. This presentation should be a particularly useful starting point for attendees new to PCI-SIG technologies.
Speaker: Richard Solomon
Richard Solomon is Technical Marketing Manager for Synopsys' PCIe Controller IP. He’s been involved in PCI chip development since the original PCI spec, co-chairs the PCI-SIG compliance workgroup, and has served on the PCI-SIG Board of Directors for some 20 years. Richard holds a BSEE from Rice University and 27 US Patents, many PCI-related.
PCI Express Basics
Tuesday, June 13 | 10:30 AM – 11:30 AM PT
Wednesday, June 14 | 9:00 AM – 10:00 AM PT
In this session, attendees learn the basics of the PCI Express Architecture. This presentation covers the key features of PCI Express and provides an overview of the Electrical, Packet-based Protocol and Configuration Mechanism of this high-performance serial bus architecture. This session is geared towards attendees new to PCI Express Technologies.
Speaker: Richard Solomon
Richard Solomon is Technical Marketing Manager for Synopsys' PCIe Controller IP. He’s been involved in PCI chip development since the original PCI spec, co-chairs the PCI-SIG compliance workgroup, and has served on the PCI-SIG Board of Directors for some 20 years. Richard holds a BSEE from Rice University and 27 US Patents, many PCI-related.
PCIe Electrical Basics
Tuesday, June 13 | 1:00 PM – 2:00 PM PT
Wednesday, June 14 | 1:30 PM – 2:30 PM PT
PCIe Electrical Basics will give the audience an overview of the physical layer specification. We will focus our discussion on target channels central to the base electrical spec development, as well as key transmitter and receiver architecture requirements. We will also discuss in depth the channel compliance simulation methodology enabled by Seasim (Statistical Channel Simulator).
Speaker: Dean Gonzales
Dean Gonzales is an Analog Design Fellow at AMD and is actively involved with circuit architecture analysis, advanced package development, system architecture and signal integrity. Dean has three decades of experience working with top tier companies including Intel, Broadcom and NASA.
Future of PCIe Technology in Emerging Markets: A Look at Our Industry
Tuesday, June 13 | 2:00 PM – 3:00 PM PT
For the past three decades, PCI-SIG® has delivered a succession of industry-leading PCI Express® (PCIe®) specifications that remain ahead of the increasing demand for a high-bandwidth, low-latency interconnect for compute-intensive systems in diverse market segments. A new PCI-SIG commissioned report from notable analyst firm ABI Research provides more information about why companies should continue investing in PCIe technology in their product roadmaps.
In this presentation from the PCI-SIG Marketing Work Group (MWG) Co-Chairs, attendees will learn the key takeaways from the new report and how PCIe technology will continue to be used in emerging markets like the data center, network edge, telecoms, artificial intelligence, automotive and mobile devices. Attendees will also learn how they can support the development and advancement of PCIe technology within PCI-SIG technical work groups and the MWG. Finally, attendees will learn how they can access the report as a member resource.
Speaker: Scott Knowlton
Scott Knowlton is the Director of Strategy in the Synopsys IP Group. He started his career as a chip designer and he has been in Synopsys Marketing since 1997. In 2003, he launched our PCIe IP and began his relationship with PCI-SIG. He has been the co-chair of the MWG since 2018.
PCI Express M.2/U.2 Updates
Tuesday, June 13 | 3:30 PM – 4:30 PM PT
Wednesday, June 14 | 2:30 PM – 3:30 PM PT
This presentation provides updates on the PCI Express M.2 and U.2 Specification development work in the PCI-SIG PCIe Mini (M.2) and SFF-8639 (U.2) workgroups resp. The presentation provides a snapshot of the changes that have been incorporated into the latest M.2/U.2 specifications. The presentation will also cover details on approved ECNs since last release of these specifications (Rev 4.0).
Speaker: Manisha Nilange
Manisha Nilange is an IO Architect and Analog Engineering Manager at Intel Corp. She has been with Intel Corp for 17 years. She leads multiple form-factor specification development, transmitter and receiver compliance test methodology and compliance tool development. Manisha chairs the CEM, Mini CEM (M.2) and SFF-8639 Connector (U.2) workgroups in PCI-SIG and co-chairs the Serial Enabling workgroup. Manisha holds MS in Electrical Engineering from the University of Texas at Arlington.
Update on MiniSAS-HD External Cables
Wednesday, June 14 | 10:30 AM – 11:30 AM PT
This presentation will provide an update on the activities within the PCI-SIG Cabling Workgroup. The information in this presentation refers to a specification that is still in the development process. All material is subject to change before specification is released, but does reflect the latest efforts, major milestones, status and projected path forward towards completing the project.
Speaker: Samuel Kocsis
Sam Kocsis currently holds the role of Director of Standards and Technology at Amphenol, focusing on the proliferation of innovative interconnect solutions. Sam coordinates Amphenol’s engagement strategies in various industry standards and consortiums across networking, server/storage, optics, and commercial markets. He is active in IEEE 802.3, OIF, and OCP projects, and is currently a co-chair of the OSFP MSA and chairman of the PCI SIG Cabling Workgroup. Sam holds BSEE and MSEE degrees from the University of Rochester, in Rochester, New York.
PCIe 5.0/6.0 Internal and External Cable Specifications
Wednesday, June 14 | 11:30 AM – 12:30 PM PT
Speaker: Mohiuddin Mazumder
Mohiuddin Mazumder is a Senior Principal Engineer in Data Center and AI division of Intel. He leads the Electrical Pathfinding and Standards Development work for high-speed differential interconnect technologies. He co-chairs the PCI-SIG Electrical WG and also leads the PCIe 5.0/6.0 Internal and External Cables specification for 32 and 64 GT/s.
Track 3 – Members Implementation
Enabling PCI Express® 6.0 IP for Interoperability and Compliance
Tuesday, June 13 | 9:30 AM – 10:30 AM PT
We present our experience in building and testing an IP subsystem for PCI Express 6.0 in 5nm with a goal of enabling interoperability testing with first silicon. We highlight clock recovery challenges and idiosyncrasies of NRZ-PAM4 transitions during PCIe® 6.0 recovery equalization and our success with Keysight’s first 6.0 exerciser platform in Root Port and Endpoint mode. We discuss PCIe Stressed Eye Test challenges in SRIS mode as the target eye height and width shrinks over PCIe rates from 16GT/s to 64GT/s. Silicon results from our implementation will be shared.
Speaker: Ali Ilhan
Ali Ulas Ilhan is a PCIe Systems and Firmware Architect at Cadence Design Systems since 2008 and has worked on PCIe since the 3.0 specification.
PCIe® Fabrics Advanced Solutions
Tuesday, June 13 | 10:30 AM – 11:30 AM PT
The server architecture is undergoing a necessary revolution to support composable component architectures that drive up component utilization. Innovations in PCI Express® Fabrics are at the forefront in helping shape this new reality today. These fabrics have the capability to dynamically reassign workloads to different compute nodes or accelerators, manage hot add/removal of endpoints, and support peer-to-peer communications all at PCIe® line rates with very low latency. This session provides a technical overview of PCIe® Fabric technology and how it delivers both disaggregation and compossibility so customers can navigate the changing landscape of the data center.
Speaker: Chetana Manjunath Kaushik
Chetana Kaushik is a senior applications engineer with the Data Center Solutions group (DCS) at Microchip. In her role, she designs and debugs PCIe® Gen 4, Gen 5, next Gen systems that utilize the latest technologies. In addition to her experience with PCIe, she works with NVMe®, C, Python and Linux®-based systems. She earned her MS degree in telecommunications engineering from University of Texas at Dallas, and she has over eight years of experience in the computer industry.
Flit FEC Analysis at PCIe 6.0 Rx Stress Test
Tuesday, June 13 | 1:00 PM – 2:00 PM PT
The Flit Base FEC adopted by PCIe 6.0 defines the Physical Layer First BER (FBER) as <E-6.
This paper analyzes the correlation between errors that cannot be corrected (uncorrectable errors) and FBER using Flit FEC and proposes a Flit FEC evaluation analysis method for the Physical Layer under worst-case Rx test conditions. It proposes some helpful chip and module-level quality improvements with respect to uncorrectable-error pattern dependency and bit-sequence repeatability.
Speaker: Hiroshi Goto
Hiroshi has over 25 years of experience as a high speed and optical Engineer at Anritsu Company holding a variety of positions including Design Engineer, Product Marketing Engineer and currently high speed and optical Product Manager and Business Development Manager.
Large Multiple Function Devices and You
Tuesday, June 13 | 2:00 PM – 3:00 PM PT
Multi-function devices have been a part of the PCI specification since its inception, but there is a growing industry trend toward much larger function counts than the original eight allowed. Devices like SmartNICs and DPUs often represent themselves as virtualized hierarchies complete with multiple virtual devices. This presentation will cover design options and implementation considerations for a variety of possible SoC design and architecture choices to allow implementing from tens to thousands of functions. In addition, it will cover the differences among, and use of, Functions, Physical Functions, Virtual Functions, and virtualized hierarchies including with the software implications of each.
Speaker: Richard Solomon
Richard Solomon is Technical Marketing Manager for Synopsys' PCIe Controller IP. He’s been involved in PCI chip development since the original PCI spec, co-chairs the PCI-SIG compliance workgroup, and has served on the PCI-SIG Board of Directors for some 20 years. Richard holds a BSEE from Rice University and 27 US Patents, many PCI-related.
Within Spec and Sanity: Tips for Electrical Characterization of PCIe
Tuesday, June 13 | 3:30 PM – 4:30 PM PT
Hardware compliance testing and characterization is an excellent way to catch hardware bugs that simulations cannot, and to stress test a system under extreme conditions. However, when confronted with a failing system or device, it can be tricky to pinpoint the issue to the test setup, software bug, or an actual design defect. This presentation will share tips on common issues found during hardware testing of PCIe and how to pinpoint their sources, best practices to mitigate human error in a lab setting, considerations for extreme temperature testing, and unique issues encountered when testing an integrated PCIe refclk.
Speaker: Heather Lothamer
Heather Lothamer is an Applications Engineer at Texas Instruments, working on Automotive Processors. She has characterized and validated several high-speed interfaces on different devices, including PCIe. She graduated with a BS in Computer Engineering from Rose-Hulman in 2016.
Noise Coupling in an IC Pinfield – A Critical Crosstalk Source
Wednesday, June 14 | 9:00 AM – 10:0 AM PT
The effective management of crosstalk is necessary to ensure reliable high-speed signaling. Accurate modeling of crosstalk sources and minimizing couplings through design optimization have become increasingly important because of the speed increase and especially the introduction of the PAM4 signaling to PCIe 6.0. Geometry details, such as the breakout traces through the via farm in an IC pinfield, can be a significant crosstalk source. We will share the modeling and measurement data for various pinfield coupling mechanisms and discuss the best design practice and optimization options to ensure high-quality PCIe channel designs and a healthy ecosystem for a stable interoperability.
Speaker: Kai Xiao
Dr. Kai Xiao is a Principal Engineer in the Data Center and AI Group at Intel Corporation. He is responsible for the interconnect solutions of high-speed differential interfaces on Intel data center and enterprise platforms.
Troubleshooting Complex LTSSM Corner Cases & Timing
Wednesday, June 14 | 10:30 AM – 11:30 AM PT
As we move to PCIe 6.0, increased data rates will present even greater interoperability challenges when bringing up links, especially where speed and timing are concerned. During link initiation, link partners follow a complex link training protocol called Link Training and Status State Machine (LTSSM). The protocol includes a state machine with multiple branching options and tight timing constraints. When LTSSM interop issues arise, it can be difficult to replicate and debug them among a myriad of potential causes.
This session will provide designers with insight and techniques on troubleshooting these complex test cases with repeatability, including debugging during LTSSM bring up, and timing testing boundary conditions with a highly configurable link partner.
Speaker: Yamini Shastry
Yamini Shastry is Director of Customer Success and responsible for ensuring VIAVI customers are fully supported on the operation and application of VIAVI Xgig protocol analysis systems. She has 20 years of software engineering experience and a MS degree in Computer Science from the University of New Hampshire.
Handling PCIe 6.0 Spec Optimizations
Wednesday, June 14 | 11:30 AM – 12:30 PM PT
PCIe 6.0 introduced substantial enhancements at all layers for lowering latency in multiple ways. Yet, they are often predicated on assumptions that, if not managed properly, could result in errors. There are several scenarios that are examined in this paper: no sync header and OS Insertion Interval counter; implicit flit sequence number and related variables; shared flow control credits and inefficient resource usage; and no lane reconfiguration in L0p upsize and parallel packet flows. Insightful information, such as implementation approaches, robust algorithms, and test scenarios, will be supplied for each to guarantee the design's intended functionality.
Speaker: Gustavo Araujo
Gustavo is a PCIe developer at Cadence Design Systems on PCIe Verification IP, with expertise in all PCIe domains, especially PCIe 6.0. He holds a bachelors degree in Electrical Engineering from Federal University of Minas Gerais, Brazil.
PLL Characterization Techniques for High Precision Measurement
Wednesday, June 14 | 1:30 PM – 2:30 PM PT
PCIe and PLL characterization have a history originating in interoperability problems attributed to phase locked loop peaking and general unconstrained PLL design in the early specs. Since this time, PLL characterization has been a core measurement in the PCI Sig's test program and has evolved over the years since it was first introduced 18 years ago. This track will review how we got to this point in the PLL interop program and the future outlook for advanced measurement techniques.
Speaker: Rick Eads
Rick is a principal program manager at Keysight Technologies with expertise in technical/industrial marketing and development of test and measurement tools and electronic design automation software in the computer, semi-conductor, communications, and storage industries. Rick provides technical leadership in driving standards within industry organizations for PCI Express, CXL, OCP, CCIX, GenZ, NVM Express, CEI 4.0, IEEE 802.3, ExpressCard, DDR, SATA, and InfiniBand. Rick holds a BSEE from Brigham Young University with an emphasis on digital design and computer architecture and an MBA from the University of Colorado. Rick actively contributes to the development of the PCIe physical layer BASE, CEM, and Test specifications and has led electrical Gold Suite testing at PCI-SIG workshops worldwide since 2004. Rick currently serves on the PCISIG Board of Directors.
Design Considerations for PCIe 6.0 Retimers
Wednesday, June 14 | 2:30 PM – 3:30 PM PT
As data rates double from PCIe 5.0 at 32GT/s to PCIe 6.0 at 64GT/s, signal integrity challenges remain a factor and retimers will continue to play a significant role in extending reach.
Attendees at this presentation will:
· Learn how retimers can help overcome signal attenuation challenges caused by channel insertion loss at PCIe 6.0 speeds
· Find out how retimers complement a switch in various applications
· Learn how SRIS and SRNS impact links and how retimers address the impact
· Understand where a retimer should be placed in the channel
· Gain insight into efforts to standardize footprints
Speaker: Casey Morrison
As Chief Product Officer, Casey Morrison has responsibility for defining products and ensuring seamless integration in customer systems. Casey’s career has centered on helping customers solve complex challenges related to high-speed serial interface design and high-bandwidth/low-latency data interconnects. Casey has presented at numerous PCI-SIG DevCons and webinars.
Track 4 – Members Implementation
Advanced Power Savings, Understanding the Basics
Tuesday, June 13 | 9:30 AM – 10:30 AM PT
This presentation will focus on explaining some of the different power saving modes as well as how to use industry tools to validate that the device is properly following these power management transitions. There will be a focus on the following:
• Explaining the L1 LTSSM state and substates
• Explaining PM D and L States
• Focus on L1 PM substates (L1.1 and L1.2)
• Explaining the L1 PM Substates Register
• Using a Protocol Analyzer and other industry tools to validate/troubleshoot Power Savings.
Speaker: David Nuttall
David Nuttall graduated from Brigham Young University with a bachelor's degree in Electrical engineering. David has been working at SerialTek for the past 12 years and is currently the Director of Engineering. During his time at SerialTek, David has been focusing on the development of PCIE protocol Analyzers.
Extending Channel Reach with Retimers – Validation & Simulation
Tuesday, June 13 | 10:30 AM – 11:30 AM PT
Retimers were first included in the PCIe 4.0 Base specification to extend the physical channel reach at 16GT/s and increasing prevalence with higher speeds and PAM4 signaling. This presentation reveals how Retimers improve signal integrity in lossy/noisy channels by reshaping analog signals, reducing signal distortion, and improve overall communication link quality. Key aspects of IBIS AMI based Retimer simulation will be reviewed and compared with the electrical validation techniques to improve pre-silicon and post-silicon correlation. The audience will gain insight into the latest tools and measurement methodologies to extend the physical reach with PCB and cabled topologies.
Speaker: David Bouse
David Bouse is a Principal Technology Leader at Tektronix with expertise in highspeed SERDES including transmitter and receiver test methodologies, digital signal processing algorithms for NRZ/PAM4 signaling, clock characterization, and automation software architecture. Pathfinding is his specialty for stressed eye calibration techniques and transmitter characterization to advance data rate speed/reliability. David supports real time oscilloscope and receiver hardware test development and is the technical leader for the Tektronix PCI Express and CXL solutions. He authored the PCI Express 4.0 Physical Layer test specification while previously at Intel, designed PCIe/USB test fixtures, and was the lead software developer for the SigTest compliance and validation tool.
Efficacious Verification of OS Error Injection in PCIe® 6.0
Tuesday, June 13 | 1:00 PM – 2:00 PM PT
Nowadays serial protocols have evolved to get the fastest and fittest throughput. This evolution increases the complexity in any serial protocol’s physical Layer. PCIe 6.0 (64 GTs) has many important features added compared to 5.0. One advantage is doubling the speed now to 64GTs. Along with doubling the speed it also introduced new OS(Order Set) TS0 and various existing OS definition has been changed. So it becomes very important we fully verify this new OS and their associated State transition. Base spec was added with Flit Error Injection capability. This capability gives user to introduce error in their transmitted and/or received Flit or OS. Because of this they can easily verify or achieve some of the corner cases. So, it becomes important to verify this Flit error injection capability. This presentation talks about the efficacious verification of Flit Error Injection Capability especially the OS Error Injection part. With the verification approach presented in presentation DUT can be tested vigorously by using CDV (constraint random verification). With approach presented in the presentation many issues were discovered. With the said approach we can reduce the verification time and effort. We also achieved 100% function coverage for the same.
Speaker: Pinal Patel
Pinal is the Associate Director at Einfochips Ltd. He has more than 15 years of experience in architecting the verification environment for SoC and IPs. he has been involved with verifying the PCIe IP since last 12 years. He has worked on all the generations of PCIe starting from 1.0 to 6.0. He has presented technical presentation at PCI-SIG DevCon before and most recent one was in Taiwan 2023.
PCIe Performance on Arm based Multi-Chip Architecture
Tuesday, June 13 | 2:00 PM – 3:00 PM PT
The infrastructure market is multiplying the server performance by scaling the number of identical dies used in the System. The Performance of Die-to-Die and Socket-to-Socket links between multiple chips are very critical in ensuring the PCIe devices in one chip efficiently communicate with a memory or device interfaced with another chip. In last year's conference the infrastructure and payloads used in the performance analysis was presented. This year's presentation walks through typical single-die, bifurcated single-die, multi-die and multi-socket SoC architectures, related PCIe performance infrastructure and how they were used to analyse performance bottlenecks.
Speaker: Bharath Venkatasubramanian
Bharath graduated from the University of York with Masters Degree in Digital Systems Engineering. He has 16+ years of experience in the VLSI, working on the verification of Client, IOT and Infrastructure system designs. He is currently working at Arm, UK working on PCIe/CXL performance analysis at the System Context.
Cable and Connector Compliance with Integrated Return Loss
Tuesday, June 13 | 3:30 PM – 4:30 PM PT
Upcoming PCIe 5.0 and 6.0 Cable and 6.0 CEM specifications are considering Integrated Return Loss (IRL) for excursion compliance. Excursions may occur as compliance further reduces noise requirements and suppliers optimize high volume manufacturing practices. Excursions up to a limit have minimal system impact. IRL is not new, it's history and process are reviewed, followed by simulation and measurement examples.
Speaker: Steve Krooswyk
Steve works on new high-speed connector development at Samtec. His 20 years of signal integrity experience has had a focus on the design, simulation, and correlation of PCIe interconnect and I/O. Previously, Steve was the PCIe tech lead for SI in Intel’s data center division during Gen3 and Gen4 development. He is an author of the book High Speed Digital Design and holds a MS degree from the University of South Carolina.
Connector and Cable Assembly Challenges for PCIe 5.0 and 6.0
Wednesday, June 14 | 9:00 AM – 10:0 AM PT
With 32 GT/s in PCIe 5.0 and 64 GT/s in PCIe 6.0, channel characteristics like loss, reflections and crosstalk are increasingly critical for the overall system performance. We will discuss performance requirements and implementations of PCIe 5.0 / 6.0 connectors and cable assemblies and the corresponding test setups and measurement methods to characterize and verify these interconnects. New metrics of ICN and IRL are included, as well as the related measurements. As the PCIe specifications define the performance requirements without the test fixtures, optimized test fixture design and accurate test fixture modelling and de-embedding is key for good measurement results. We will preview modern de-embedding techniques with accurate impedance modelling of lead-ins and lead-outs.
Speaker: Martin Stumpf
Martin Stumpf is Segment Manager for High-Speed Digital Test at Rohde & Schwarz. He joined Rohde & Schwarz in 1990 as R&D engineer and has worked in research & development, project management, product management, regional support and business development. Martin holds an EE degree from Technical University of Munich.
Data Driven Insights into Stressed Eye Solution Space
Wednesday, June 14 | 10:30 AM – 11:30 AM PT
The PCI Express Physical Layer Electrical testing requires testing receiver performance using a worst-case transmitter and channel. Establishing this "Stressed Eye Signal" involves a complex calibration procedure quantified with an eye diagram measurement using the latest DSP techniques. The final step in this calibration starts with nominal stress levels and requires adjustment of cross talk, modelled with Differential Mode Interference or DMI, and Sinusoidal Jitter (SJ) to fine tune the eye within a tight tolerance. Legacy data rates have relied on DMI and SJ to impact the vertical and horizontal eye closure respectively. New interactions and dependencies at 32 GT/s have led to a pronounced interdependence impacting the methods used to achieve this signal. This paper will analyze empirical data to provide insight into the shape of the solution space and guidance for future development at 64 GT/s.
Speaker: Joey Chiu
Joey Chiu is a Product Applications Engineer with Tektronix. He has over 10 years of experience working in the test and measurement industry and has been working on PCI Express technology and test solution for the past 4 years. Joey received both MS and BS in Mechanical Engineering from National Taiwan University.
Don’t Be Intimidated: Manual Calibration for Stressed Eye Testing
Wednesday, June 14 | 11:30 AM – 12:30 PM PT
The automated Rx Stressed Eye Test calibration packages provided by test vendors have become popular due to their convenience and efficiency. It is important for engineers to perform the manual calibration at least once to gain a more comprehensive understanding of the Rx stressed eye test calibration results. This presentation goes step-by-step through the manual Rx stressed eye test calibration procedure. This presentation also demonstrates an alternative channel calibration method that modifies the definition and measurement of the calibration channel.
Speaker: Ahmed Sada
Ahmed Sada is a Staff Silicon Validation Engineer at Synopsys and has 9 years of experience in the field of electrical testing and validation of SerDes IP. Ahmed serves as the technical lead for silicon debug and validation activities for the PCIe product line, and he collaborates with different design teams to co-ordinate test methodologies and design-for-test enhancements
PCIe and Optics: Are we ready
Wednesday, June 14 | 1:30 PM – 2:30 PM PT
Optical solutions have been demonstrated as a viable part of the PCIe ecosystem for almost two decades, but typical implementations were closed systems which required customized features to fit into PCIe platforms. As the PCI SIG investigates 128GT/s, the performance of passive copper may be becoming limited, yet cabling between network elements is proving to be more critical as disaggregated architectures become more prevalent. This presentation highlights the need for standardizing PCIe cabling solutions to expand beyond passive copper, provides details for the functional and architectural support that may be needed, and provides examples of form factors which address the issues.
Speaker: Samuel Kocsis
Sam Kocsis currently holds the role of Director of Standards and Technology at Amphenol, focusing on the proliferation of innovative interconnect solutions. Sam coordinates Amphenol’s engagement strategies in various industry standards and consortiums across networking, server/storage, optics, and commercial markets. He is active in IEEE 802.3, OIF, and OCP projects, and is currently a co-chair of the OSFP MSA and chairman of the PCI SIG Cabling Workgroup. Sam holds BSEE and MSEE degrees from the University of Rochester, in Rochester, New York.