Richard Solomon

Richard Solomon is Technical Marketing Manager for Synopsys' PCIe Controller IP.  He’s been involved in PCI chip development since the original PCI spec, co-chairs the PCI-SIG compliance workgroup, and has served on the PCI-SIG Board of Directors for some 20 years. Richard holds a BSEE from Rice University and 27 US Patents, many PCI-related.

PCI Express Basics & Background 

In this session, attendees learn the basics of the PCI Express Architecture. This presentation covers the key features of PCI Express and provides an overview of the Electrical, Packet-based Protocol and Configuration Mechanism of this high-performance serial bus architecture. This session is geared towards attendees new to PCI Express Technologies. 

Eugene Sushansky

Eugene is Vice President of Global Engineering at Granite River Labs Inc. (GRL). He has been in the industry for over 29 years, 14 of that at GRL, where he focuses in leading testing services for various High-Speed interconnects. Prior to joining GRL, Eugene has worked for OSZ Storage Solutions Inc. (Kioxia), and PLX Technology Inc. (Broadcom). He provides technical leadership in many industry standards including PCI Express and SATA. Eugene earned BSEE from San Francisco State University with an emphasis on digital design and computer architecture.

PCIe 6.0 Electrical Update

In this presentation, we will provide an overview of updates to the specification of Reference Clock, Transmitter, Receiver, and Channel Compliance for PCIe 6.0 64 GT/s data rate. We will highlight the key improvements in circuit and channels required for achieving doubling of the data rate over PCIe 5.0.
 

PCIe Electrical Basics

PCIe Electrical Basics will give the audience an overview of the physical layer specification. We will focus our discussion on target channels central to the base electrical spec development, as well as key transmitter and receiver architecture requirements. We will also discuss in depth the channel compliance simulation methodology enabled by Seasim (Statistical Channel Simulator).

Manisha Nilange

Manisha Nilange is a Principal Engineer at Intel Corp. She has been with Intel Corp for 18 years. She leads multiple form-factor specification development, transmitter and receiver compliance test methodology and compliance tool development. Manisha chairs the PCI Express Card Electromechanical (CEM), PCI Express Mini (M.2) and PCI Express SFF Connector (U.2) workgroups in PCI-SIG and co-chairs the Serial Enabling workgroup. Manisha holds MS in Electrical Engineering from the University of Texas at Arlington.

PCIe Form-Factor Updates

This presentation provides updates on the PCI Express CEM specification, PCI Express Mini (M.2) specification and PCI Express SFF Connector (U.2) specification development work in respective PCI-SIG workgroups. The presentation focuses on an overview of the changes introduced in Rev 5.0 of the specifications and related ECRs. The presentation will also provide an update on the current workgroup direction for Rev 6.0 Specification development that will add support for 64 GT/s. This includes Add-in Card outline updates, sideband interfaces and connector signal integrity optimizations.

Paul Cassidy

Paul Cassidy is a Senior R&D Manager for Synopsys’ DesignWare PCI Express Controller IP, based in Dublin, Ireland. With 20 years of industry experience, Paul has worked on the architecture and design of Synopsys PCI Express controller since joining Synopsys in 2009. Paul has a BEng from University College Cork.

PCIe 6.0 Protocol Update

This session covers PCI Express protocol developments over the last year or two, including completed ECNs, selected ECRs under development, and major protocol/spec changes in PCIe 6.0.  Completed ECNs include Combined Power and Relaxed Detect Timing.  Selected ECRs under development include TEE Device Interface Security Protocol (TDISP), DOE 1.1, CMA Update, ATS 2.0, and Unordered I/O (UIO).  Major protocol/spec changes for PCIe 6.0 include Flit Mode, Segment Support in Flit Mode, L0p replacing L0s in Flit Mode, Shared Flow Control Credits, 14-Bit Tags in Flit Mode, Max_Payload_Size enhancements, Deprecated features, and Improved SR-IOV spec integration.

Debendra Das Sharma 

Dr. Debendra Das Sharma is an Intel Senior Fellow and co-GM of Memory and I/O Technologies,  Data Platforms and Artificial Intelligence Group, at Intel Corporation. He is a leading expert on I/O subsystem and interface architecture. He delivers Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCIe), and Intel’s Coherency interconnect, as well as their implementation. 
 

PCIe 6.0 PHY Logical

PCI Express (PCIe) specification has been doubling the data rate every generation in a backwards compatible manner every two to three years. PCIe 6.0 specification has adopted PAM-4 signaling at 64.0 GT/s for maintaining the same channel reach as prior generations. A forward error correction (FEC) mechanism will offset the high BER of PAM-4. A new Flit-based approach with a light-weight, low-latency FEC coupled with a strong CRC and a low-latency link level retry mechanism in PCIe 6.0 specification meets the stringent low-latency, high bandwidth and high reliability goals. Shared credit pooling across multiple virtual channels is included to reduce the area and power overhead while providing the necessary quality of service guarantees. We also present a new low-power state (L0p) that ensures power consumption is proportional to bandwidth usage without impacting the traffic flow.

Yamini Shastry

Yamini Shastry leads the Customer Success team and is responsible for ensuring VIAVI customers are fully supported on the operation and application of VIAVI Xgig protocol analysis systems.  She has years of software engineering experience with expertise in building and delivering test and analysis solutions for high-speed protocols. 

Troubleshooting LTSSM Transactions and Timing in PCIe 6.0

During link initiation, link partners follow a complex link training protocol called LTSSM.  The protocol includes multiple branching state machines and tight timing constraints. When LTSSM interop issues arise, it can be difficult to replicate them among a myriad of potential causes. PCIe 6.0 introduces FLIT mode negotiations, TS0 and L0p states to LTSSM, and new OS patterns for transitions to/from L0 states. 
This session will provide designers with insight and techniques for troubleshooting these complex transactions with repeatability, including debugging during bring-up and testing boundary conditions with a highly configurable link partner.

Sai Prakash Seethaka

Sai Prakash Seethaka, Senior Systems Design Engineer at Xilinx-AMD, brings five years of expertise in PCIe, DMA, and system-level validation. An award-winning and highly recognized innovator, he excels in pre- and post-silicon validation, with a keen focus on PCIe/CXL interactions within SoCs.

Validation of System Level PCIe Ordering Rules 

As PCIe evolves to meet higher performance demands, optimizing hardware and software for concurrent memory and configuration traffic while adhering to PCIe ordering rules is crucial. Ensuring data integrity and system consistency is key. Validation must ensure that performance improvements do not breach PCIe’s ordering specifications or compromise data consistency, avoiding issues like deadlock, livelock, or starvation. Interactions with other protocols, such as AXI, and components like bridges and cache-coherency interconnects can introduce ordering problems. Effective validation is essential for managing these interactions and maintaining performance. This presentation will outline a strategy to identify such issues early in the program cycle.

Urvi Mehta 

Urvi Mehta is ASIC Digital Design Engineer with Synopsys for > 6 years of experience in the field of Design Verification. Urvi has worked on Testchip development and verification for Serdes phy on different PCIe products supporting PCIe-Gen5/6 and E112/224G.She collaborates with different design and validation teams to co-ordinate test methodologies.

Demonstrating Key PCIe 6 SerDes Metrics without FEC

PCIe 6.0 deploys lightweight Forward Error Correction (FEC) with Flow Control Unit (FLIT) encoding. The proposal aims to compute flit retry rate and post FEC-Bit error rate at physical layer without FEC block. Data processed from physical layer’s enhanced Bit Error Rate Tester at flit level analyzes error distribution from predictable pseudorandom binary sequence stream. Extracted results are checked and if higher than threshold value, frequency of continuous calibration and adaption can be increased to improve channel performance and hence, improve QoR. This proposal offers real-time error rate trends and sets benchmark for PCIe6 SERDES PHY performance without additional hardware circuitry.

Ritesh Metha

Ritesh Mehta is working as a design verification engineer with Google for more than a year. I have an experience of around six years ad have been working with PCIe for more than 2 years. At Google I am part of the team which is working on verifying a PCIe sub-system. 

Challenges of Partial Header Encryption in PCIe 6.x

PCIe 6.0 introduces Partial Header Encryption (PHE), enhancing Integrity and Data Encryption (IDE) by selectively encrypting IDE Memory request headers while preserving TLP routing and essential low-level information. This paper discusses the advantages of PHE, provides practical implementation guidance for integrating PHE into existing IDE modules, and analyzes the specific effects of PHE on TLP rules in both Flit Mode (FM) and Non-Flit Mode (NFM). Additionally, it addresses challenges after PHE integration, crucial verification considerations, presents pointers for enabling PHE across different data streams, explores dependencies on IDE fields like Plaintext CRC (PCRC), and discusses potential extensions of PHE to Compute Express Link (CXL.io) mode.

Deep Metha

Deep Mehta is VerificationIP Product Engineer at Cadence Design Systems at Ahmedabad. He has 14+ years of experience in Verification & Validation Profile; Experienced at Verification IP development and deployment.

Effective PCIe 6.x Switch Performance Verification 

As PCIe 6.0 adoption grows, switch translation logic between FM and NFM TLP formats poses a significant performance risk. Traditional data integration testing falls short in detecting these penalties. To verify all switch ports with FM and NFM mode traffic, performance testing strategies must be evaluated against different speed, link width, and TLP traffic generation. In this paper, we showcase few scenarios where design-induced penalties occur and introduce innovative utilities - Performance Banner and Flit TLP Tracker - to identify elusive bugs beyond Flit Performance Measurement capability, which is only valid for FM.

Suprio Biswas

Suprio Biswas is working as Lead Member Technical Staff in Questa Verification IP team of Siemens EDA. He has completed his B.Tech in Electronics and Communication Engineering from Netaji Subhas Institute of Technology. He has more than 4 years of working experience in PCIe Gen5 and 6 VIPs

Exploring Verification Challenges of Shared Flow Control

This paper elaborates on the use case of Shared Flow Control and its associated verification challenges. Requirement of Shared Flow Control 1. Enables sharing of buffer space across VC for efficient space and area management. 2. Introduction of Optimized UpdateFC, Credit Merging and dedicated credits for better performance and throughput of the PCIe link. Shared Flow Control Verification Scenarios 1. Transmission of TLPs using both Shared and Dedicated Credits. 2. Completely utilizing the shared pool of any credit type across all the enabled VCs by any single VC without updating the buffer limit 3. Checking of credits by enabling/disabling multiple VCs dynamically. 4. Scenarios involving the Credit Merging and Shared FC Usage Limit.