PCI-SIG Developers Conference Asia-Pacific Tour 2019 Agenda
Tokyo, Japan
Wednesday, October 23, 2019
Time | Title |
---|---|
8:00 am - 9:00 am | Registration |
9:00 am - 10:30 am | PCI Express Basics & Background |
10:30 am - 11:00 am | AM Break and Exhibit |
11:00 am - 12:30 pm | PCIe 5.0 Electrical Update |
12:30 pm - 1:30 pm | Lunch and Exhibit |
1:30 pm - 2:30 pm | PCIe CEM 5.0 Previews |
2:30 pm - 3:30 pm | PCIe 5.0 Protocol Update |
3:30 pm - 4:00 pm | PM Break and Exhibit |
4:00 pm - 5:00 pm | PCIe 5.0 PHY Logical |
5:00 pm - 6:00 pm | PCIe Compliance Updates |
Taipei, Taiwan
Monday, October 28, 2019 – Day 1
Time | Title |
---|---|
8:00 am - 9:00 am | Registration |
9:00 am - 10:30 am | PCI Express Basics & Background |
10:30 am - 11:00 am | AM Break and Exhibit |
11:00 am - 12:15 pm | PCIe 5.0 Electrical Update |
12:15 pm - 1:15 pm | Lunch and Exhibit |
1:15 pm - 2:15 pm | PCIe CEM 5.0 Previews |
2:15 pm - 3:15 pm | PCIe 5.0 Protocol Update |
3:15 pm - 3:45 pm | PM Break and Exhibit |
3:45 pm - 4:45pm | PCIe 5.0 PHY Logical |
4:45 pm - 5:45 pm | PCIe Compliance Updates |
Tuesday, October 29, 2019 – Day 2
Time | Title |
---|---|
9:00 am - 10:00 am | Correlating Methods and Demystifying 32GT/s Receiver Testing |
10:00 am - 10:30 am | AM Break & Exhibit |
10:30 am - 11:30 am | PCI Express Link Training and Protocol Debug Techniques |
11:30 pm - 12:30 pm | PCIe Architectures for Chip-to-Chip Interconnects |
12:30 pm - 1:30 pm | Lunch & Exhibit |
1:30 pm - 2:30 pm | PCB Bandwidth Analysis for PCIe at 16GT/s and 32GT/s |
2:30 pm - 3:30 pm | Enable PCIe 5.0 System Design with Ethernet Architectures |
3:30 pm - 4:00 pm | PM Break and Exhibit |
4:00 pm - 5:00 pm | PCIe DUT Receiver Margin Assessment with BERT Sinusoidal Jitter Injection |