PCI-SIG Developers Conference APAC Tour 2024 Agenda

Tokyo, Japan

Wednesday, February 14, 2024
8:30 am – 9:30 am Registration & Breakfast
9:30 am  – 11:00 am  PCI Express Basics & Background 
11:00 am – 12:00 pm PCIe 6.0 Electrical Update 
12:00 pm – 1:00 pm Lunch & Exhibit
1:00 pm – 2:00 pm PCIe CEM Updates
2:00 pm – 3:00 pm PCIe 6.0 Protocol Update 
3:00 pm – 3:30 pm PM Break & Exhibit
3:30 pm – 4:30 pm PCIe 6.0 PHY Logical 
4:30 pm – 5:30 pm PCIe Compliance Updates

Taipei, Taiwan 

Day One – Monday, February 19, 2024
8:30 am – 9:30 am Registration & Breakfast
9:30 am  – 11:00 am  PCI Express Basics & Background 
11:00 am – 12:00 pm PCIe 6.0 Electrical Update 
12:00 pm – 1:00 pm Lunch & Exhibit
1:00 pm – 2:00 pm PCIe CEM Updates
2:00 pm – 3:00 pm PCIe 6.0 Protocol Update 
3:00 pm – 3:30 pm PM Break & Exhibit
3:30 pm – 4:30 pm PCIe 6.0 PHY Logical 
4:30 pm – 5:30 pm PCIe Compliance Updates
Day Two - Tuesday, February 20, 2024
8:30 am – 9:30 am                                       Registration & Breakfast
9:30 am – 10:30 am PCI Express 6.0 Protocol Troubleshooting and Debug
10:30 am – 11:00 am  AM Break & Exhibit
11:00 am – 12:00 pm Large Multiple Function Devices and You
12:00 pm  – 1:00 pm  Lunch & Exhibit 
1:00 pm – 2:00 pm PCIe 6.0 RAS Technology and Fault Isolation Case Study
2:00 pm – 3:00 pm PCIe Retimer Telemetry for RAS on Cloud Compute System
3:00 pm – 3:30 pm  PM Break & Exhibit 
3:30 pm – 4:30 pm Efficacious Verification of OS Error Injection in PCIe 6.0
4:30 pm – 5:30 pm PCIe 6.0 Verification Challenges and Solutions


Speakers and Abstracts 

Paul Cassidy

Paul Cassidy is a Senior R&D Manager for Synopsys’ DesignWare PCI Express Controller IP, based in Dublin, Ireland. With 20 years of industry experience, Paul has worked on the architecture and design of Synopsys PCI Express controller since joining Synopsys in 2009. Paul has a BEng from University College Cork.

PCIe 6.0 Protocol Update

This session covers PCI Express protocol developments over the last year or two, including completed ECNs, selected ECRs under development, and major protocol/spec changes in PCIe 6.0.  Completed ECNs include Combined Power and Relaxed Detect Timing.  Selected ECRs under development include TEE Device Interface Security Protocol (TDISP), DOE 1.1, CMA Update, ATS 2.0, and Unordered I/O (UIO).  Major protocol/spec changes for PCIe 6.0 include Flit Mode, Segment Support in Flit Mode, L0p replacing L0s in Flit Mode, Shared Flow Control Credits, 14-Bit Tags in Flit Mode, Max_Payload_Size enhancements, Deprecated features, and Improved SR-IOV spec integration.

PCIe 6.0 PHY Logical

PCI Express (PCIe) specification has been doubling the data rate every generation in a backwards compatible manner every two to three years. PCIe 6.0 specification has adopted PAM-4 signaling at 64.0 GT/s for maintaining the same channel reach as prior generations. A forward error correction (FEC) mechanism will offset the high BER of PAM-4. A new Flit-based approach with a light-weight, low-latency FEC coupled with a strong CRC and a low-latency link level retry mechanism in PCIe 6.0 specification meets the stringent low-latency, high bandwidth and high reliability goals. Shared credit pooling across multiple virtual channels is included to reduce the area and power overhead while providing the necessary quality of service guarantees. We also present a new low-power state (L0p) that ensures power consumption is proportional to bandwidth usage without impacting the traffic flow.

Gordon Getty

Gordon is Technical Marketing Manager at Teledyne LeCroy. He has been working on PCI Express technologies for 22 years. Gordon is an active contributor to the PCI Express Test Specifications. Gordon graduated from Glasgow University with a Bachelor’s degree in Electronics and Music and a MSc in Information Technology from the University of Paisley.

PCI Express 6.0 Protocol Troubleshooting and Debug

The PCI Express 6.0 specification enables many new capabilities including the 64GT/s data rate using PAM4 signaling. These changes require significant changes to the protocol layers to support the new signaling. This presentation will discuss changes to Link Training including Equalization protocol, and also the changes to the Data Link Layer and Transaction Layer when the link is operating in both Flit mode and Non-Flit mode. The presentation will also discuss key techniques to assist in analyzing, troubleshooting and debugging systems and endpoints designed to the PCIe 6.0 specification.

Wayne Huang

Wayne is Intel High-Speed IO Technical Lead, Validation Architect in Data Center AI Division. He leads HSIO technologies platform validation debug. With +25 years of industry experience, Wayne has worked on silicon design and server platform technologies and architecture in x86 industry. Wayne holds a MS degree from Syracuse University.

PCIe 6.0 RAS Technology and Fault Isolation Case Study

PCIe 6.0 provides compatible error handling and support advanced error classification, signaling, logging, and reporting. It improves fault isolation and recovery solutions with integrated hardware and software. This session covers PCIe 6.0 RAS features update, the error handling process, and PCIe fault isolation case study. With error propagation flow, we can take advantage of the header of a received TLP that incurs an unmasked, uncorrectable error by fine tuning error handling and fault recovery flow settings to achieve fault isolation. The case study provides a real case to narrow down the SW driver fault that results in PCIe Completer Abort.

Liang Lu

Liang is Asia FAE Lead at Astera Labs and responsible for supporting customers in Taiwan, China, etc. He has 15+ years of high-speed interface product experience including system design, application support and product definition. He enjoys addressing signal integrity challenges on various high-speed interfaces using Astera Labs’ retimers.

PCIe Retimer Telemetry for RAS on Cloud Compute System

PCIe is a major interconnect in hyperscale cloud datacenter systems. The ability to monitor, identify, and fix problems with minimal effect on the end user becomes more essential as the speed and number of PCIe links increase. PCIe Retimers are uniquely positioned between Root Complex and Endpoints and can thus offer telemetry capabilities to monitor and identify potential failures during system activity. Attendees will learn: 1. How PCIe Retimers can help identify Link reliability issues at cloud-scale. 2. Types of parameters a Retimer can extract from the PCIe Link and interconnect. 3. Why time stamping is important, and how time stamps are captured.

Mohiuddin Mazumder

Mohiuddin Mazumder is a Senior Principal Engineer in Data Center and AI division of Intel. He leads the Electrical pathfinding and Standards development work for high-speed differential interconnect technologies. He co-chairs the PCI-SIG Electrical WG and also leads the PCIe 5.0/6.0 Internal and External Cables specification for 32 and 64 GT/s.

PCIe 6.0 Electrical Update

In this presentation, we will provide an overview of updates to the specification of Reference Clock, Transmitter, Receiver, and Channel Compliance for PCIe 6.0 64 GT/s data rate. We will highlight the key improvements in circuit and channels required for achieving doubling of the data rate over PCIe 5.0.

Xin Mu

Xin Mu, Sr. Solution Manager from Cadence Design System, with 10-year of industry experience. Skilled in PCIe, CCIX, CXL, and Verification IP solutions and methodologies. Strong engineering professional with Leading and supporting PCIe Verification IP and family products to deliver the best customer success.

PCIe 6.0 Verification Challenges and Solutions

PCIe PCIe 6.0 introduces several changes across all layers. It has disrupted the existing design flow, thus making the verification critical and challenging. This paper mainly touches upon challenges and corresponding solutions in three areas. Flit: Implicit sequence number in the Flit packets, Flit retry buffer to attain the original size of TLP, unpredictable Standard NAK or Selective NAK.  Training Sequence TS0/TS1/TS2: New TS0 type with DC-balance and Parity handling, halves validation for mirrored values, new symbol position, backward compatibility for 8b/10b and block encoding in FLIT mode. L0p: The new low power state maintains at least one active lane, verifying different ordered sets combination on deactivated and reactivated lanes during downsizing and upsizing.

Manisha Nilange

Manisha Nilange is an IO Architect and Analog Engineering Manager at Intel Corp. She has been with Intel Corp for 17 years. She leads multiple form-factor specification development, transmitter and receiver compliance test methodology and compliance tool development. Manisha chairs the CEM, Mini CEM (M.2) and SFF-8639 Connector (U.2) workgroups in PCI-SIG and co-chairs the Serial Enabling workgroup. Manisha holds MS in Electrical Engineering from the University of Texas at Arlington.

PCIe CEM Updates 

This presentation provides updates on the PCI Express CEM specification development work in the PCI-SIG Electromechanical Workgroup. The presentation focuses on providing an overview of the changes introduced in PCI Express Card Electromechanical Specification, Rev 5.0 (CEM 5.0) and related ECRs. The presentation also provides an overview of several potential improvements under investigation for CEM 6.0. This includes Add-in Card outline updates, sideband interfaces and connector optimizations. 

PCIe Compliance Updates

The PCI-SIG has introduced the 5.0 Integrators List program with a new maximum data rate of 32 GT/s enabling a bi-direction link bandwidth up to 128 GB/s for a x16 link. The PCI Express Architecture PHY Test Specification Rev 5.0 has updated the 16 GT/s tests to support the faster rate and introduced new testing requirements including uncorrelated jitter and pulse width jitter for all 5.0 devices. Discussion of measurement methodologies for Tx Signal Quality and Link Equalization testing will provide insight into the latest measurement methodologies.

Pinal Patel

Pinal is the Associate Director at Einfochips Ltd. He has more than 15 years of experience in architecting the verification environment for SoC and IPs. He has been involved with verifying the PCIe IP since last 10 years. He has worked on all the generations of PCIe starting from 1.0 to 6.0. He has presented technical presentation at PCI-SIG DevCon before.

Efficacious Verification of OS Error Injection in PCIe 6.0

Nowadays serial protocols have evolved to get the fastest and fittest throughput. This evolution increases the complexity in any serial protocol’s physical Layer. PCIe 6.0 (64 GTs) has many important features added compared to 5.0. One advantage is doubling the speed now to 64GTs. Along with doubling the speed it also introduced new OS(Order Set) TS0 and various existing OS definition has been changed. So it becomes very important we fully verify this new OS and their associated State transition. Base spec was added with Flit Error Injection capability. This capability gives user to introduce error in their transmitted and/or received Flit or OS. Because of this they can easily verify or achieve some of the corner cases. So, it becomes important to verify this Flit error injection capability. This presentation talks about the efficacious verification of Flit Error Injection Capability especially the OS Error Injection part. With the verification approach presented in presentation DUT can be tested vigorously by using CDV (constraint random verification). With approach presented in the presentation many issues were discovered. With the said approach we can reduce the verification time and effort. We also achieved 100% function coverage for the same.

Richard Solomon

Richard Solomon is Technical Marketing Manager for Synopsys' PCIe Controller IP.  He’s been involved in PCI chip development since the original PCI spec, co-chairs the PCI-SIG compliance workgroup, and has served on the PCI-SIG Board of Directors for some 20 years. Richard holds a BSEE from Rice University and 27 US Patents, many PCI-related.

PCI Express Basics & Background 

In this session, attendees learn the basics of the PCI Express Architecture. This presentation covers the key features of PCI Express and provides an overview of the Electrical, Packet-based Protocol and Configuration Mechanism of this high-performance serial bus architecture. This session is geared towards attendees new to PCI Express Technologies. 

Large Multiple Function Devices and You

Multi-function devices have been a part of the PCI specification since its inception, but there is a growing industry trend toward much larger function counts than the original eight allowed.  Devices like SmartNICs and DPUs often represent themselves as virtualized hierarchies complete with multiple virtual devices.  This presentation will cover design options and implementation considerations for a variety of possible SoC design and architecture choices to allow implementing from tens to thousands of functions.  In addition, it will cover the differences among, and use of, Functions, Physical Functions, Virtual Functions, and virtualized hierarchies including with the software implications of each.