The “Meet the PCI-SIG® Members” blog series is a way to highlight our diverse global members that make PCI-SIG what it is today. PCI-SIG members help to advance and promote PCI Express® (PCIe®) technology innovation in the industry, while receiving a variety of benefits.

FMS: The Future of Memory and Storage is quickly approaching on Aug. 6-8, 2024, at the Santa Clara Convention Center, and has expanded its scope to encompass all tiers of Memory and Storage.

There are many unique challenges in designing artificial intelligence (AI) and machine learning (ML) applications, and the exuberance around ChatGPT has highlighted the influence that AI can have on day-to-day life.

Author’s Note: This blog discusses new functionality introduced in the PCIe 6.0 specification, but please note that subsequent revisions have been published. Developers should always work from the latest revision to ensure they see all specification errata.

Infographic of the PCIe 6.0 Architecture

The upcoming PCIe® 6.0 specification introduces Flow Control Unit (FLIT) encoding, which enables the specification to provide low latency with high efficiency. FLIT mode is adopted for the PCIe 6.0 architecture because error correction needs to operate on fixed sized packets.

The upcoming PCI Express^® (PCIe^®) 6.0 specification will continue PCI-SIG’s^® longstanding history of innovation for the next generation of products to keep up with evolving needs in a wide range of markets.

One of the many new features included in the PCI Express^® (PCIe^®) specification will be PAM4 (Pulse Amplitude Modulation with 4 levels) signaling.

For almost two decades, the PCI Express^® (PCIe^®) architecture has offered low latency and high bandwidth in support of next generation systems.

We are starting 2020 with the release of version 0.5 of the PCI Express^® (PCIe^®) 6.0 specification incorporating the significant member feedback received on version 0.3.