Wow, 2020 sure has transformed the ways we connect, learn and innovate in industries around the world, and in our daily lives!

The PCI Express^® (PCIe^®) 6.0 specification will feature two primary mechanisms to correct errors: Forward Error Correction (FEC) and Cyclic Redundancy Check (CRC). Each 256-byte FLIT comprises of 242 bytes of payload which are protected by 8 Bytes of CRC.

The upcoming PCI Express^® (PCIe^®) 6.0 specification will continue PCI-SIG’s^® longstanding history of innovation for the next generation of products to keep up with evolving needs in a wide range of markets.

One of the many new features included in the PCI Express^® (PCIe^®) specification will be PAM4 (Pulse Amplitude Modulation with 4 levels) signaling.

PCI-SIG^® has shifted to virtual events for the 2020 calendar year and our first major members event was the Virtual PCI-SIG Developers Conference.

For almost two decades, the PCI Express^® (PCIe^®) architecture has offered low latency and high bandwidth in support of next generation systems.

PCI Express^® (PCIe^®) technology is the most important high-speed serial bus in servers. Due to its high bandwidth and low latency characteristics, PCI Express architecture is widely used in various server interconnect scenarios, such as:

Before the emergence of autonomous driving, our cars provided isolation from the outside world. We could move from point A to point B with the press of a pedal and a Mapquest print-out in the passenger seat.

Before the emergence of autonomous driving, our cars provided isolation from the outside world. We could move from point A to point B with the press of a pedal and a Mapquest print-out in the passenger seat.

Each year, over 800 PCI-SIG^® member companies are invited to attend the PCI-SIG U.S. Developers Conference.