PCI-SIG specifications define standards driving the industry-wide compatibility of peripheral component interconnects. Members regularly review them, providing commentary and change requests when necessary. These requests are considered by technical workgroups and applied as appropriate, resulting in collaboratively devised specifications benefiting millions of platforms and add-in devices.
Engineering Change Request Process
PCI-SIG members may submit requests to change specifications here. The Engineering Change Request process and form can be found here.
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PCI Code & ID Assignment Specifications
The PCI Code & ID Assignment Specifications are accessible to non-members without charge here. PCI-SIG members can download these specifications directly from the Specifications Library below.
This document is a companion specification to the PC...view moreThis document is a companion specification to the PCI Express Base Specification and other PCI Express® documents listed in Section 1.1. The primary focus of the PCI Express OCuLink Specification is the implementation of internal and external small form factor PCI Express connectors and cables. This form factor supports multiple market segments, from client, mobile, server, datacenter, and storage. This specification discusses cabling and connector requirements to meet the 8.0 GT/s signaling needs in the PCI Express Base Specification.
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DISCLAIMER: Table A-1, Bytes 0 to 1...view moreDISCLAIMER: Table A-1, Bytes 0 to 127 (Lower Memory Fields), contained an error in the 1.0 Specification. Byte 0, Identifier, was 0Eh and has been changed to 1Ch.
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This is a modification of the cable assembly memory ...view moreThis is a modification of the cable assembly memory map defined in the OCuLink Memory Map ECN. Some bits contained within the external cable assembly's memory are modified to allow for cable aggregation.
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This is a modification of the cable assembly memory ...view moreThis is a modification of the cable assembly memory map defined in the OCuLink Memory Map ECN. Some bits contained within the external cable assembly's memory are modified to allow for cable aggregation.
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Several dimensions included in Chapter 9 of the OCuL...view moreSeveral dimensions included in Chapter 9 of the OCuLink 1.0 Specification are repeated from previous chapters. 7 Repeated dimensions have been removed and additional pointers have been added to direct users where to find 8 more information about various OCuLink implementations.
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Drawings and dimensions for the x4 form factor have ...view moreDrawings and dimensions for the x4 form factor have been corrected and clarified.
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The cable presence (CPRSNT#) signal was incompletely...view moreThe cable presence (CPRSNT#) signal was incompletely and inaccurately specified in the original OCuLink 1.0 specification. The definition for the logic levels of this signal contradicted the active low naming convention. The direction has multiple contradictions.
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The OCuLink workgroup has received feedback that the...view moreThe OCuLink workgroup has received feedback that the information included in the specification regarding cable/ Port aggregation was unclear, particularly with respect to sideband management. Wording in sections relating to cable/ Port aggregation and sideband management has been reworked to be clearer.
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The ECN provides clarif...view moreThe ECN provides clarifications for requirements that affect both systems implementers and cable assembly suppliers. The revisions will save time and confusion for the implementation of the optional external OCuLink cables.show less
The IL/ fitted IL requirements have been clarified....view moreThe IL/ fitted IL requirements have been clarified. The language of this portion of the spec has been reworked to eliminate confusion and provide uniformity in the subsections included in the following document.
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The IL/ fitted IL requirements have been clarified....view moreThe IL/ fitted IL requirements have been clarified. The language of this portion of the spec has been reworked to eliminate confusion and provide uniformity in the subsections included in the following document.
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This is a modification of the connector/cable perfor...view moreThis is a modification of the connector/cable performance tables defined in OCuLink 1.0, Section 6.9 and updated by the OCuLink Server Change ECN. The tables are reorganized to make this section of OCuLink more functional to the end user. Some table entry values are changed.
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a....view morea. The connector and cable assembly pinout tables have been revised to show the complete OCuLink pinout assignments in all cases. b. The two left-most columns in the cable pinout tables have been combined for clarity. c. Due to the fact that the pinout tables span multiple pages, P1/P2 designations have been included in the appropriate column titles of the cable pinout tables to make it easier to follow which end of the cable is being addressed on each page in each table.
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The backplane type (BP Type) signal was incompletely...view moreThe backplane type (BP Type) signal was incompletely specified in the original OCuLink 1.0 specification. Table 2-2 now includes a Type of logic used for this signal. A definition is provided for the logic levels of this signal.
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a....view morea. The connector and cable assembly pinout tables have been revised to show the complete
OCuLink pinout assignments in all cases.
b. The two left-most columns in the cable pinout tables have been combined for clarity.
c. Due to the fact that the pinout tables span multiple pages, P1/P2 designations have been
included in the appropriate column titles of the cable pinout tables to make it easier to follow
which end of the cable is being addressed on each page in each table.
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The backplane type (BP Type) signal was incompletely...view moreThe backplane type (BP Type) signal was incompletely specified in the original OCuLink 1.0 specification. Table 2-2 now includes a Type of logic used for this signal. A definition is provided for the logic levels of this signal.
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A PCI Express Receiver is required to tolerate 6 ns ...view moreA PCI Express Receiver is required to tolerate 6 ns of lane to lane skew when operating at 8.0 GT/s. The PCI Express OCuLink Specification allowed the cable assembly to consume the entire budget. The Transmitter and traces routing to the OCuLink connector need some of this budget. The PCI Express Card Electromechanical Specification Revision 3.0 assigns 1.6 ns to the total interconnect lane to lane skew budget.
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Table 6-12 and Table 6-13 in Section 6.9 are modifie...view moreTable 6-12 and Table 6-13 in Section 6.9 are modified to reflect connector requirements for server/datacenter segment. In addition, this proposal also reflects a clarification in the Introduction text, Section 1 to include the server/datacenter market segment.
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This is a modification of the cable assembly memory ...view moreThis is a modification of the cable assembly memory map defined in OCuLink 1.0, Appendix A. The addresses for the data bytes contained within the external cable assembly's memory will be reorganized. In addition, some data in these fields are modified.
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This document is a companion Specification to the PC...view moreThis document is a companion Specification to the PCI Express Base Specification and other PCI Express® 2 documents listed in Section 1.1. The primary focus of the PCI Express OCuLink Specification is the implementation 3 of internal and external small form factor PCI Express® connectors and cables optimized for the client and mobile 4 market segments. This Specification discusses cabling and connector requirements to meet the 8.0 GT/s signaling 5 needs in the PCI Express Base Specification. 6
No assumptions are made regarding the implementation of PCI Express compliant components on either side of 7 the Link; such components are addressed in other PCI Express Specifications.
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