This specification contains the Class Code and Capab...view moreThis specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. It is intended that this document be used along with the PCI Express Base Specification Revision 5.0.
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This specification contains the Class Code and Capab...view moreThis specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. It is intended that this document be used along with the PCI Express Base Specification Revision 5.0.
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This specification contains the Class Code and Capab...view moreThis specification contains the Class Code and Capability ID descriptions originally contained the
PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and
maintain. This specification also consolidates Extended Capability ID assignments from the PCI
Express Base Specification and various other PCI specifications.
It is intended that this document be used along with the PCI Express Base Specification Revision
5.0.
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Defines a new wire semantic and related capabilities...view moreDefines a new wire semantic and related capabilities for addressing the limitations of the PCI/PCIe fabric-enforced ordering rules. Specifically: Fabrics with multiple paths between a source and destination cannot be supported; posted Writes don’t match the semantics of other fabrics, in that the Requester doesn’t (directly) know if/when a write has actually completed; and writes flowing towards destinations with differing write performance can cause global stalls
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This proposal introduces a new version of the M.2 co...view moreThis proposal introduces a new version of the M.2 connector with improved amperage per pin to 1A, and card outline changes with increased component area options.
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This specification contains the Class Code and Capab...view moreThis specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. It is intended that this document be used along with the PCI Express Base Specification Revision 5.0.
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This ECR defines a revised and extended Data Object ...view moreThis ECR defines a revised and extended Data Object Exchange mechanism. This ECN builds 5 upon the content defined in the ECN that defined the original revision of Data Object Exchange, published 26 March 2020 (document date of 12 March 2020).
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This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the
programming interface required to design and build systems and peripherals that are compliant with the PCI Express
Specification. This document defines the “base” specification for the PCI Express architecture, including the electrical, protocol,
platform architecture and programming interface elements required to design and build devices and systems.
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This is a change bar version of the PCI Express Base...view moreThis is a change bar version of the PCI Express Base 6.0 Specification comparing Base 6.0/1.0 to Base 6.0.1/1.0
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...view more
Expansion of example methods for lane margining testing to create different electrical link conditions for the two test runs. These changes apply to both Add-in Card and System testing.
Adding a repeatability test option as proof that lane margining measurement is implemented.
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This specification contains the Class Code and Capab...view moreThis specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications.
It is intended that this document be used along with the PCI Express Base Specification Revision 5.0.
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Revision B (July 22, 2020) corrects an errata in the...view moreRevision B (July 22, 2020) corrects an errata in the original revision (November 28, 2018). PWRDIS timings were incorrectly specified as a maximum when they are meant to be specified as a minimum value. The affected portion is highlighted in Table 3-26 PWRDIS AC characteristics.
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This document is a companion specification to the PC...view moreThis document is a companion specification to the PCI Express Base Specification and other PCI Express® documents listed in Section 1.1. The primary focus of the PCI Express OCuLink Specification is the implementation of internal and external small form factor PCI Express connectors and cables. This form factor supports multiple market segments, from client, mobile, server, datacenter, and storage. This specification discusses cabling and connector requirements to meet the 8.0 GT/s signaling needs in the PCI Express Base Specification.
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This specification contains the Class Code and Capab...view moreThis specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications.
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DISCLAIMER: Table A-1, Bytes 0 to 1...view moreDISCLAIMER: Table A-1, Bytes 0 to 127 (Lower Memory Fields), contained an error in the 1.0 Specification. Byte 0, Identifier, was 0Eh and has been changed to 1Ch.
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This ECN introduces multiple features for M.2 and af...view moreThis ECN introduces multiple features for M.2 and affects the PCIe M.2 Specification Revision 1.1 and the PCIe BGA SSD 11.5x13 ECN.
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Several dimensions included in Chapter 9 of the OCuL...view moreSeveral dimensions included in Chapter 9 of the OCuLink 1.0 Specification are repeated from previous chapters. 7 Repeated dimensions have been removed and additional pointers have been added to direct users where to find 8 more information about various OCuLink implementations.
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Drawings and dimensions for the x4 form factor have ...view moreDrawings and dimensions for the x4 form factor have been corrected and clarified.
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The cable presence (CPRSNT#) signal was incompletely...view moreThe cable presence (CPRSNT#) signal was incompletely and inaccurately specified in the original OCuLink 1.0 specification. The definition for the logic levels of this signal contradicted the active low naming convention. The direction has multiple contradictions.
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The OCuLink workgroup has received feedback that the...view moreThe OCuLink workgroup has received feedback that the information included in the specification regarding cable/ Port aggregation was unclear, particularly with respect to sideband management. Wording in sections relating to cable/ Port aggregation and sideband management has been reworked to be clearer.
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The ECN provides clarif...view moreThe ECN provides clarifications for requirements that affect both systems implementers and cable assembly suppliers. The revisions will save time and confusion for the implementation of the optional external OCuLink cables.show less
This change notice redefines the outer most ring of ...view moreThis change notice redefines the outer most ring of ground pins in the 11.5x13 BGA ball map to be redundant ground pins that are non-critical to function (NCTF).NCTF is a new pin definition indicating that while the pins shall continue to be connected to host and device ground, they are redundant such that they allow for mechanical failure but not functional failure.
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The IL/ fitted IL requirements have been clarified....view moreThe IL/ fitted IL requirements have been clarified. The language of this portion of the spec has been reworked to eliminate confusion and provide uniformity in the subsections included in the following document.
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The IL/ fitted IL requirements have been clarified....view moreThe IL/ fitted IL requirements have been clarified. The language of this portion of the spec has been reworked to eliminate confusion and provide uniformity in the subsections included in the following document.
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This is a modification of the connector/cable perfor...view moreThis is a modification of the connector/cable performance tables defined in OCuLink 1.0, Section 6.9 and updated by the OCuLink Server Change ECN. The tables are reorganized to make this section of OCuLink more functional to the end user. Some table entry values are changed.
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The M.2 Type 1216 Land Grid Array (LGA) Connectivity...view moreThe M.2 Type 1216 Land Grid Array (LGA) Connectivity module is modified to add a second PCIe lane. Referring to Figure 99 on page 127
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This proposal adds an additional voltage value to th...view moreThis proposal adds an additional voltage value to the PWR_1 rail in the PCIe BGA SSD 11.5x13 ECR. Table 3 of section 3.4 in the document “PCIe BGA SSD 11.5x13 ECR”, defines the PWR_1 signal as a 3.3V source. This is changed to now also include a 2.5V rail.
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The backplane type (BP Type) signal was incompletely...view moreThe backplane type (BP Type) signal was incompletely specified in the original OCuLink 1.0 specification. Table 2-2 now includes a Type of logic used for this signal. A definition is provided for the logic levels of this signal.
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a....view morea. The connector and cable assembly pinout tables have been revised to show the complete
OCuLink pinout assignments in all cases.
b. The two left-most columns in the cable pinout tables have been combined for clarity.
c. Due to the fact that the pinout tables span multiple pages, P1/P2 designations have been
included in the appropriate column titles of the cable pinout tables to make it easier to follow
which end of the cable is being addressed on each page in each table.
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The backplane type (BP Type) signal was incompletely...view moreThe backplane type (BP Type) signal was incompletely specified in the original OCuLink 1.0 specification. Table 2-2 now includes a Type of logic used for this signal. A definition is provided for the logic levels of this signal.
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a....view morea. The connector and cable assembly pinout tables have been revised to show the complete OCuLink pinout assignments in all cases. b. The two left-most columns in the cable pinout tables have been combined for clarity. c. Due to the fact that the pinout tables span multiple pages, P1/P2 designations have been included in the appropriate column titles of the cable pinout tables to make it easier to follow which end of the cable is being addressed on each page in each table.
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M.2 Key B (WWAN) is modified to enable PCIe and USB ...view moreM.2 Key B (WWAN) is modified to enable PCIe and USB 3.1 Gen1 signals to be simultaneously present on the connector. This enables support for a single SKU M.2 card that supports both PCIe and USB 3.1 Gen1. There are two implementation options enabled:
1. State #14 in the “Socket 2 Add-in Card Configuration Table” is re-defined to indicate an Add-in Card built to the PCI Express M.2 Specification, Revision 1.1 or later where both PCIe and USB 3.1 Gen1 are both present on the connector. The choice of Port Configuration is vendor defined. This enables the host to unambiguously determine that PCIe and USB 3.1 Gen1 are present on the connector.
2. States #4, 5, 6, 7 in the “Socket 2 Add-in Card Configuration Table” are re-defined to indicate that in addition to USB 3.1 Gen1, PCIe may be present on the connector. This definition was used by M.2 cards built to the PCI Express M.2 Specification, Revision 1.0 (USB 3.1 Gen1 on connector; PCIe is “no connect”). This definition is now also permitted to be used by M.2 cards built to PCI Express M.2 Specification, Revision 1.1 or later to indicate that PCIe and USB 3.1 Gen1 are both present on the connector. This allows GPIO port configurations to remain consistent with all other existing states.
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This proposal adds a new 11.5 mm x 13 mm PCIe BGA SS...view moreThis proposal adds a new 11.5 mm x 13 mm PCIe BGA SSD form factor to the M.2 v1.1 specification.
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A PCI Express Receiver is required to tolerate 6 ns ...view moreA PCI Express Receiver is required to tolerate 6 ns of lane to lane skew when operating at 8.0 GT/s. The PCI Express OCuLink Specification allowed the cable assembly to consume the entire budget. The Transmitter and traces routing to the OCuLink connector need some of this budget. The PCI Express Card Electromechanical Specification Revision 3.0 assigns 1.6 ns to the total interconnect lane to lane skew budget.
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The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini 3 Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in 4 both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and 5 higher integration of functions onto a single form factor module solution.
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The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini 3 Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in 4 both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and 5 higher integration of functions onto a single form factor module solution.
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This is a modification of the cable assembly memory ...view moreThis is a modification of the cable assembly memory map defined in OCuLink 1.0, Appendix A. The addresses for the data bytes contained within the external cable assembly's memory will be reorganized. In addition, some data in these fields are modified.
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Table 6-12 and Table 6-13 in Section 6.9 are modifie...view moreTable 6-12 and Table 6-13 in Section 6.9 are modified to reflect connector requirements for server/datacenter segment. In addition, this proposal also reflects a clarification in the Introduction text, Section 1 to include the server/datacenter market segment.
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This specification defines an implementation for sma...view moreThis specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified subset of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 2.0. Where this specification 5 does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs.
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This specification defines an implementation for sma...view moreThis specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified subset of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 2.0. Where this specification 5 does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs.
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This ECN is intended to define a new form-factor and...view moreThis ECN is intended to define a new form-factor and electrical pinout to the M.2 family. This proposal will allow PCIe and SATA to be delivered using a BGA package, expanding the use of the PCIe and SATA protocols in small form-factor applications. The new BGA pinout content is based on the Socket 3 Key-M definitions. BGA pinout supports additional pins than defined for Socket-3, for soldered-down form-factors.
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This document is a companion Specification to the PC...view moreThis document is a companion Specification to the PCI Express Base Specification and other PCI Express® 2 documents listed in Section 1.1. The primary focus of the PCI Express OCuLink Specification is the implementation 3 of internal and external small form factor PCI Express® connectors and cables optimized for the client and mobile 4 market segments. This Specification discusses cabling and connector requirements to meet the 8.0 GT/s signaling 5 needs in the PCI Express Base Specification. 6
No assumptions are made regarding the implementation of PCI Express compliant components on either side of 7 the Link; such components are addressed in other PCI Express Specifications.
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This ECR describes the necessary changes to enable a...view moreThis ECR describes the necessary changes to enable a new WWAN Key C definition to be included as an addition to the existing spec. The intent is to create a dedicated WWAN socket Key and pinout definition. This new pinout definition will be focused on WWAN specific interfaces and needs.
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In ECN “Power-up requirements for PCIe side bands (P...view moreIn ECN “Power-up requirements for PCIe side bands (PERST#, etc.)” - submitted by Dave Landsman and Ramdas Kachare - section 3.1.3.2.1 is redefined to provide a more realistic timing model for reset.
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The proposed change is to include 2 GNSS Aiding sign...view moreThe proposed change is to include 2 GNSS Aiding signals, that we already have allocated in the Type 1216 pinout, to the Socket 1 Key E pinout and Type 2226/3026 pinout. Due to lack of free pins in the Key E pinout, it is proposed to define 2 SDIO Input signals as dual functional pins. They would be defined with their original SDIO functionality along with and alternate GNSS Aiding signals functionality to enable a GNSS solution on Type 2230 solutions on Socket 1 Key E solutions. The GNSS signals to be added are the Tx Blanking and SYSCLK signals and it is suggested to overlay them on the SDIO RESET# and SDIO CLK respectively which are also inputs. In this way it is less likely to cause a potential contention.
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Definition of two of the three COEX pins as a UART T...view moreDefinition of two of the three COEX pins as a UART Tx/Rx communication path between Socket 1 and Socket 2 in favor of WWAN ßà Connectivity coexistence. The intent is to definitively define the location of the source and sink sides of the signal path.
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The proposed change is to change the current voltage...view moreThe proposed change is to change the current voltage level of the NFC related signals (I2C DATA, I2C CLK and ALERT#) on the Connectivity pinouts and definitions from 3.3V to 1.8V signal level to better align with future platforms operating signal levels typical in the industry.
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Section 3.1.3.2.1 is redefined to provide a more rea...view moreSection 3.1.3.2.1 is redefined to provide a more realistic timing model for reset.
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Definition of the four Audio pins to provide definit...view moreDefinition of the four Audio pins to provide definitive functions assigned to each pin of the Audio interface.
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SMBus interface signals are included in sections 3.2...view moreSMBus interface signals are included in sections 3.2 and 3.3 and related minor clarifications added to sections 1.2, 1.3, 2.2, 4.1, 4.2, 5.2.2, and 5.3.
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Mobile broadband peak data rates continue to increas...view moreMobile broadband peak data rates continue to increase. With LTE category 5, USB 2.0 will not meet the performance requirements. LTE category 5 peak data rates are 320 Mbps downlink; 75 Mbps uplink. Most USB 2.0 implementations achieve a maximum of about 240 Mbps throughput. Looking longer term, the ITU has set a target of 1 Gbits/s for low mobility applications for IMT Advanced.
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Modify the Mini Card specification to tighten the po...view moreModify the Mini Card specification to tighten the power rail voltage tolerance.
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The M.2 form factor is used for Mobile Add-In cards....view moreThe M.2 form factor is used for Mobile Add-In cards. The M.2 is a natural transition from the Mini Card and Half-Mini Card to a smaller form factor in both size and volume. The M.2 is a family of form factors that will enable expansion, contraction, and higher integration of functions onto a single form factor module solution.
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This document primarily covers PCI Express testing o...view moreThis document primarily covers PCI Express testing of root complexes, switches, bridges, and endpoints for the standard configuration mechanisms, registers, and features in Chapter 7 of the PCI Express Base Specification, Revision 2.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.
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This document primarily covers PCI Express testing o...view moreThis document primarily covers PCI Express testing of root complexes, switches, bridges, and endpoints for the standard configuration mechanisms, registers, and features in Chapter 7 of the PCI Express Base Specification, Revision 2.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.
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This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building add-in cards or system boards to the PCI Express Card Electromechanical Specification, Revision 2.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.
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This test specification primarily covers testing of ...view moreThis test specification primarily covers testing of all PCI Express Port types for compliance with the link layer requirements in Chapter 3 of the PCI Express Base Specification. At this point, this specification does not describe the full set of PCI Express tests for all link layer requirements. Going forward, as the testing gets mature, it is expected that more tests may be added as deemed necessary.
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This is a companion specification to the PCI Express...view moreThis is a companion specification to the PCI Express Base Specification. Its primary focus is the implementation of cabled PCI Express®. The discussions are confined to copper cabling and their connector requirements to meet the PCI Express signaling needs at 5.0 GT/s. No assumptions are made regarding the implementation of PCI Express compliant Subsystems on either side of the cabled Link; e.g., PCI Express Card Electromechanical (CEM), ExpressCard5 ™, ExpressModule™, PXI Express™, system board, or any other form factor. Such form factors are covered in other separate specifications.
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This is a companion specification to the PCI Express...view moreThis is a companion specification to the PCI Express Base Specification. Its primary focus is the implementation of cabled PCI Express®. The discussions are confined to copper cabling and their connector requirements to meet the PCI Express signaling needs at 5.0 GT/s. No assumptions are made regarding the implementation of PCI Express compliant Subsystems on either side of the cabled Link; e.g., PCI Express Card Electromechanical (CEM), ExpressCard5 ™, ExpressModule™, PXI Express™, system board, or any other form factor. Such form factors are covered in other separate specifications.
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Modify the PCI Express Mini Card specification to de...view moreModify the PCI Express Mini Card specification to define a new interface for tunable antennas. Modify the PCI Express Mini Card specification to enable existing coexistence signals to operate simultaneously with new tuneable antenna control signals.
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This specification defines an implementation for sma...view moreThis specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 2.0. Where this specification does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs.
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This specification defines an implementation for sma...view moreThis specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 2.0. Where this specification does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs.
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The Process Address Space ID (PASID) ECN to the Base...view moreThe Process Address Space ID (PASID) ECN to the Base PCI Express Specification defines the PASID TLP Prefix. This companion ECN is optional normative and defines PASID TLP Prefix usage rules for ATS and PRI.
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This optional normative ECN defines an End-End TLP P...view moreThis optional normative ECN defines an End-End TLP Prefix for conveying additional attributes associated with a request. The PASID TLP Prefix is an End-End TLP Prefix as defined in the PCI Express Base Specification. Routing elements that support End-End TLP Prefixes (i.e. have the End-End TLP Prefix Supported bit Set in the Device Capabilities 2 register) can correctly forward TLPs containing a PASID TLP Prefix.
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This ECR requests making a change to the CLKREQ# ass...view moreThis ECR requests making a change to the CLKREQ# asserted low to clock active timing when latency tolerance reporting is supported and enabled for the function. The change would be to allow this specified value to exceed 400ns up to a limit consistent with the latency value established by the Latency Tolerance Reporting (LTR) mechanism.
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This ECN is for the functional addition of a second ...view moreThis ECN is for the functional addition of a second wireless disable signal (W_DISABLE2#) as a new definition of Pin 51 (Reserved). When this optional second wireless disable signal is not implemented by the system, the original intent of a single wireless disable signal disabling all radios on the add-in card when asserted is still required.
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The purpose of this document is to specify PCI™ I/O ...view moreThe purpose of this document is to specify PCI™ I/O virtualization and sharing technology. The specification is focused on single root topologies; e.g., a single computer that supports virtualization technology.
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The purpose of this document is to specify PCI™ I/O ...view moreThe purpose of this document is to specify PCI™ I/O virtualization and sharing technology. The specification is focused on single root topologies; e.g., a single computer that supports virtualization technology.
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ECR covers proposed modification of Section 4.2 Pow...view more ECR covers proposed modification of Section 4.2 Power Consumption within the CEM Specification version 2.0.
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Prior to this ECN, all PCIe external Links were requ...view morePrior to this ECN, all PCIe external Links were required to support ASPM L0s. This ECN changes the Base Specification to permit ASPM L0s support to be optional unless the applicable formfactor specification explicitly requires it.
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This ECR proposes to add a new mechanism for platfor...view moreThis ECR proposes to add a new mechanism for platform central resource (RC) power state information to be communicated to Devices. This mechanism enables Optimized Buffer Flush/Fill (OBFF) by allowing the platform to indicate optimal windows for device bus mastering & interrupt activity. Devices can use internal buffering to shape traffic to fit into these optimal windows, reducing platform power impact.
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This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
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This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
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This specification describes the extensions required...view moreThis specification describes the extensions required to allow PCI Express Devices to interact with an address translation agent (TA) in or above a Root Complex (RC) to enable translations of DMA addresses to be cached in the Device. The purpose of having an Address Translation Cache (ATC) in a Device is to minimize latency and to provide a scalable distributed caching solution that will improve I/O performance while alleviating TA resource pressure. This specification must be used in conjunction with the PCI Express Base Specification, Revision 1.1, and associated ECNs.
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Emerging usage model trends indicate a requirement f...view moreEmerging usage model trends indicate a requirement for increase in header size fields to provide additional information than what can be accommodated in currently defined TLP header sizes. The TLP Prefix mechanism extends the header size by adding DWORDS to the front of headers that carry additional information.
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This ECN modifies the system board transmitter path ...view moreThis ECN modifies the system board transmitter path requirements (VTXS and VTXS_d) at 5 GT/s. As a consequence the minimum requirements for the add-in card receiver path sensitivity at 5 GT/s are also updated.
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This optional normative ECR defines a mechanism by w...view moreThis optional normative ECR defines a mechanism by which a Requester can provide hints on a per transaction basis to facilitate optimized processing of transactions that target Memory Space. The architected mechanisms may be used to enable association of system processing resources (e.g. caches) with the processing of Requests from specific Functions or enable optimized system specific (e.g. system interconnect and Memory) processing of Requests.
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The change allows a Function to use Extended Tag fie...view moreThe change allows a Function to use Extended Tag fields (256 unique tag values) by default; this is done by allowing the Extended Tag Enable control field to be set by default.
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This document primarily covers PCI Express testing o...view moreThis document primarily covers PCI Express testing of root complexes, switches, bridges, and endpoints for the standard configuration mechanisms, registers, and features in Chapter 7 of the PCI Express Base Specification, Revision 2.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.
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This ECR proposes to add a new mechanism for Endpoin...view moreThis ECR proposes to add a new mechanism for Endpoints to report their service latency requirements for Memory Reads and Writes to the Root Complex such that central platform resources (such as main memory, RC internal interconnects, snoop resources, and other resources associated with the RC) can be power managed without impacting Endpoint functionality and performance.
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This document contains a list of Test Assertions and...view moreThis document contains a list of Test Assertions and a set of Test Definitions pertaining to the Transaction Layer. Assertions are statements of spec requirements which are measured by the algorithm details as specified in the Test Definitions. “Basic Functional Tests” are Test Algorithms which perform basic tests for key elements of Transaction Layer device functionality. This document does not describe a full set of PCI Express tests and assertions and is in no way intended to measure products for full design validation. Tests described here should be viewed as tools to checkpoint the result of product validation – not as a replacement for that effort.
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This ECN proposes to add a new ordering attribute wh...view moreThis ECN proposes to add a new ordering attribute which devices may optionally support to provide enhanced performance for certain types of workloads and traffic patterns. The new ordering attribute relaxes ordering requirements between unrelated traffic by comparing the Requester/Completer IDs of the associated TLPs.
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DPA (Dynamic Power Allocation) extends existing PCIe...view moreDPA (Dynamic Power Allocation) extends existing PCIe device power management to provide active (D0) device power management substates for appropriate devices, while comprehending existing PCIe PM Capabilities including PCI-PM and Power Budgeting.
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The purpose of this document is to specify PCI® I/O ...view moreThe purpose of this document is to specify PCI® I/O virtualization and sharing technology. The specification is focused on multi-root topologies; e.g., a server blade enclosure that uses a PCI Express® Switch-based topology to connect server blades to PCI Express Devices or PCI Express to-PCI Bridges and enable the leaf Devices to be serially or simultaneously shared by one or more System Images (SI). Unlike the Single Root IOV environment, independent SI may execute on disparate processing components such as independent server blades.
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This optional normative ECN adds Multicast functiona...view moreThis optional normative ECN adds Multicast functionality to PCI Express by means of an Extended Capability structure for applicable Functions in Root Complexes, Switches, and components with Endpoints. The Capability structure defines how Multicast TLPs are identified and routed. It also provides means for checking and enforcing send permission with Function-level granularity. The ECN identifies Multicast errors and adds an MC Blocked TLP error to AER for reporting those errors.
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PCI Express (PCIe) defines error signaling and loggi...view morePCI Express (PCIe) defines error signaling and logging mechanisms for errors that occur on a PCIe interface and for errors that occur on behalf of transactions initiated on PCIe. It does not define error signaling and logging mechanisms for errors that occur within a component or are unrelated to a particular PCIe transaction.
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This optional ECN adds a capability for Functions wi...view moreThis optional ECN adds a capability for Functions with BARs to report various options for sizes of their memory mapped resources that will operate properly. Also added is an ability for software to program the size to configure the BAR to.
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This optional normative ECN defines 3 new PCIe trans...view moreThis optional normative ECN defines 3 new PCIe transactions, each of which carries out a specific Atomic Operation (“AtomicOp”) on a target location in Memory Space. The 3 AtomicOps are FetchAdd (Fetch and Add), Swap (Unconditional Swap), and CAS (Compare and Swap). FetchAdd and Swap support operand sizes of 32 and 64 bits. CAS supports operand sizes of 32, 64, and 128 bits.
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The main objective of this specification is to suppo...view moreThe main objective of this specification is to support PCI Express® add-in cards that require higher power than specified in the PCI Express Card Electromechanical Specification and the PCI Express x16 Graphics 150W-ATX Specification.
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This specification defines an implementation for sma...view moreThis specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 1.1. Where this specification does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs.
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This specification defines an implementation for sma...view moreThis specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 1.1. Where this specification does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs.
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The purpose of this document is to specify PCI™ I/O ...view moreThe purpose of this document is to specify PCI™ I/O virtualization and sharing technology. The specification is focused on single root topologies; e.g., a single computer that supports virtualization technology.
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For virtualized and non-virtualized environments, a ...view moreFor virtualized and non-virtualized environments, a number of PCI-SIG member companies have requested that the current constraints on number of Functions allowed per multi-Function Device be increased to accommodate the needs of next generation I/O implementations. This ECR specifies a new method to interpret the Device Number and Function Number fields within Routing IDs, Requester IDs, and Completer IDs, thereby increasing the number of Functions that can be supported by a single Device.
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This specification is a companion for the PCI Expres...view moreThis specification is a companion for the PCI Express Base Specification, Revision 2.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express® Mini Card are covered in other separate specifications.
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This specification is a companion for the PCI Expres...view moreThis specification is a companion for the PCI Express Base Specification, Revision 2.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express® Mini Card are covered in other separate specifications.
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This specification describes the extensions required...view moreThis specification describes the extensions required to allow PCI Express Devices to interact with an address translation agent (TA) in or above a Root Complex (RC) to enable translations of DMA addresses to be cached in the Device. The purpose of having an Address Translation Cache (ATC) in a Device is to minimize latency and to provide a scalable distributed caching solution that will improve I/O performance while alleviating TA resource pressure. This specification must be used in conjunction with the PCI Express Base Specification, Revision 1.1, and associated ECNs.
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This is a companion specification to the PCI Express...view moreThis is a companion specification to the PCI Express Base Specification. Its primary focus is the implementation of cabled PCI Express®. The discussions are confined to copper cabling and their connector requirements to meet the PCI Express signaling needs at 2.5 GT/s. No assumptions are made regarding the implementation of PCI Express compliant Subsystems on either side of the cabled Link; e.g., PCI Express Card Electromechanical (CEM), ExpressCard™, ExpressModule™, PXI Express™, system board, or any other form factor. Such form factors are covered in other separate specifications.
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This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
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This specification is a companion for the PCI Expres...view moreThis specification is a companion for the PCI Express Base Specification, Revision 1.1. Its primary focus is the implementation of an evolutionary strategy with the current PCI desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express Mini Card are covered in other separate specifications.
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This specification is a companion for the PCI Expres...view moreThis specification is a companion for the PCI Express Base Specification, Revision 1.1. Its primary focus is the implementation of an evolutionary strategy with the current PCI desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express Mini Card are covered in other separate specifications.
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This specification describes the PCI Express archite...view moreThis specification describes the PCI Express architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express specification.
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This specification describes the PCI Express archite...view moreThis specification describes the PCI Express architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express specification.
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This document is a companion specification to the PC...view moreThis document is a companion specification to the PCI Express Base Specification. Its primary focus is the implementation of a modular I/O form factor that is focused on the needs of workstations and servers from mechanicals and electrical requirements. The discussions are confined to the modules and their chassis slots requirements. Other form factors are covered in other separate specifications.
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The objectives of this specification are Support for...view moreThe objectives of this specification are Support for PCI Express™ graphics add-in cards that are higher power than specified in the PCI Express Card Electromechanical Specification, Forward looking for future scalability, Allow evolution of the PC architecture including graphics, Upgradeability, and Enhanced end user experience.
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This addendum to the PCI Express Base 1.0a describes...view moreThis addendum to the PCI Express Base 1.0a describes a low power extension intended primarily to support the reduced power requirements of mobile platforms. Its scope is restricted to the electrical layer and corresponds to Section 4.3 of PCI Express Base 1.0a.
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This specification describes the PCI Express to PCI/PCI-X bridge (also referred to herein as PCI Express bridge) architecture, interface requirements, and the programming model.
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