This proposal modifies portions of the M.2 spec to i...view moreThis proposal modifies portions of the M.2 spec to include optional I3C interface overlayed on the SMBus interface. This proposal closely follows Ch-12 from the Base specification revision 6.2.
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This is a companion specification to the PCI Express...view moreThis is a companion specification to the PCI Express Base Specification. The primary focus of this specification is the implementation of cabled PCI Express® . No assumptions are made regarding the implementation of PCI Express-compliant Subsystems on either side of the cabled Link (PCI Express Card Electromechanical (CEM), ExpressCard™, ExpressModule™, PXI Express™, or any other form factor). Such form factors are covered in separate specifications.
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The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution. One of the goals for M.2 is to be significantly smaller in the XYZ and overall volume than the HalfMini Card for the very thin computing Platforms (e.g., Notebook, Tablet/Slate Platforms) that require a much smaller solution.
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This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 5.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.
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The focus of this specification is on PCI Express® (...view moreThe focus of this specification is on PCI Express® (PCIe®) solutions utilizing the SFF-8639 (also known as U.2) connector interface. Form factors include, but are not limited to, those described in the SFF-8201 Form Factor Drive Dimensions Specification. Other form factors, such as PCI Express Card Electromechanical are documented in other independent specifications.
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This test specification is intended to confirm if a ...view moreThis test specification is intended to confirm if a stand-alone Retimer is compliant to the PCIe Base Specification. This test specification is not intended to test Retimers based only on the Extension Devices ECN to the PCI Express Base Specification, Revision 3.x. This test specification only covers stand-alone Retimers in common clock mode, and is not intended to test Retimers integrated onto a platform or an add-in card.
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This ECR introduces updated dimensioning and toleran...view moreThis ECR introduces updated dimensioning and tolerances for the 48VHPWR header and plug. The 48VHPWR connector has been removed from the specification. The name for the new connector is 48V1x2. Ordering of the sense pins is changed so that Sense0 and Sense1 pins are located farthest from each other. This reordering is incompatible with the pre-existing connector definition. Per workgroup input, there are no known implementations of the 48VHPWR header and plug as of this publication date. References to external specifications are added.
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This Card Electromechanical (CEM) specification is a...view moreThis Card Electromechanical (CEM) specification is a companion for the PCI Express® Base Specification, Revision 5.0. Its primary focus is the implementation of an evolutionary strategy with earlier PCI™ desktop/server mechanical and electrical specifications.
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This Card Electromechanical (CEM) specification is a...view moreThis Card Electromechanical (CEM) specification is a companion for the PCI Express® Base Specification, Revision 5.0. Its primary focus is the implementation of an evolutionary strategy with earlier PCI™ desktop/server mechanical and electrical specifications.
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Informational testing on test case 54-20 will give D...view moreInformational testing on test case 54-20 will give DUT vendor information about their implementation of the capability. Not passing judgement on test case 54-20 will prevent DUTs from incorrect failing the DUT or false passing the DUT at Compliance Workshops.
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The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution.
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This ECR removes the transmitter jitter test require...view moreThis ECR removes the transmitter jitter test requirement for 32 GT/s systems. Transmitter jitter test remains a requirement for 32 GT/s Add-in Cards.
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This ECN replaces existing drawings for the 12VHPWR ...view moreThis ECN replaces existing drawings for the 12VHPWR cable plug with 2 different options.
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Expands power excursion to 12V power rail in PCIE CE...view moreExpands power excursion to 12V power rail in PCIE CEM connector in addition to 12VHPWR and 48VHPWR connectors but excludes legacy 2x3 and 2x4 auxiliary power connectors from power excursion specification.
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This document defines the TEE Device Interface Secur...view moreThis document defines the TEE Device Interface Security Protocol (TDISP) - An architecture for trusted I/O virtualization providing the following functions: 1. Establishing a trust relationship between a TVM and a device. 2. Securing the interconnect between the host and device. 3. Attach and detach a TDI to a TVM in a trusted manner.
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Summary of the Functional Changes...view moreSummary of the Functional Changes
Changing the RFU pin in the 12VHPWR connector sideband to Sense1. Adding 150W and 300W power capabilities to the encoding options for Sense0 and Sense1. Makes Card_CBL_PRES required to be tied to ground with 4.7 kΩ resistor.
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Transmitter jitter requirements at 32 GT/s are being...view moreTransmitter jitter requirements at 32 GT/s are being added for system board and Add-in Card.
Affected Document: PCI Express Card Electromechanical Specification Revision 5.0, Version 1.0
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This test specification primarily covers testing of ...view moreThis test specification primarily covers testing of PCI Express® Device and Port types for compliance with the link layer and transaction layer requirements of the PCI Express Base Specification.
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This document primarily covers PCI Express testing o...view moreThis document primarily covers PCI Express testing of all defined Device Types and RCRBs for the standard Configuration Space mechanisms, registers, and features.
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This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 5.0.
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This is a change bar version of the Integrity and Da...view moreThis is a change bar version of the Integrity and Data Encryption (IDE) ECN – Revision A.
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Original IDE ECN plus IDE items included in final Ba...view moreOriginal IDE ECN plus IDE items included in final Base 5.0 Errata. Changebar version relative to original IDE ECN also available.
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The long-standing requirement for a component’s LTSS...view moreThe long-standing requirement for a component’s LTSSM to enter Detect state within 20 ms of the end of Fundamental Reset is relaxed (extended) to 100 ms for components that support >5 GT/s Link speeds.
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This change allows for cards to exceed maximum power...view moreThis change allows for cards to exceed maximum power levels currently defined in the CEM spec to enable higher performance for certain workloads. This change clearly defines limits for these excursions to allow system designers to properly design power subsystems to enable these excursions.
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Introduces a fitting-based Tx preset measurement met...view moreIntroduces a fitting-based Tx preset measurement methodology that extracts Tx equalization coefficients from measured step responses with and without Tx equalization. Consequently, it overcomes a few limitations of the current DC voltage-level based methodology where the ratio of DC voltage levels of various presets is used to avoid measurement complexity due to high frequency-dependent loss. Since the use of the ratio of DC voltage levels do not guarantee the correct use of Tx equalization coefficients and constant voltage swing across presets, the existing DC voltage-level based measurement methodology may give incorrect results if the Tx equalization coefficients and voltage swing significantly deviate from the intended values for the specified Tx presets.
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Describes a method to measure Tx jitter parameters a...view moreDescribes a method to measure Tx jitter parameters at 32 GT/s accurately by using a Jitter Measurement Pattern. This replaces the S-parameter de-embedding method. In this method, a CTLE-based equalization instead of S-parameter based de-embedding gain filter is applied to the captured Tx waveform to mitigate signal degradation due to frequency-dependent channel loss. The CTLE-based equalization is defined by the 32 GT/s reference CTLE curves. The proposed method with the use of clock pattern in the lane under test and compliance pattern in other lanes avoids the inaccuracy of the S-parameter based de-embedding that results from the amplification of the real-time oscilloscope floor noise by the de-embedding gain filter. The Tx jitter measurement methods for 8.0 and 16.0 GT/s have been kept unchanged.
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This Card Electromechanical (CEM) specification is a...view moreThis Card Electromechanical (CEM) specification is a companion for the PCI Express® Base Specification, Revision 5.0. Its primary focus is the implementation of an evolutionary strategy with earlier PCI™ desktop/server mechanical and electrical specifications.
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This Card Electromechanical (CEM) specification is a...view moreThis Card Electromechanical (CEM) specification is a companion for the PCI Express® Base Specification, Revision 5.0. Its primary focus is the implementation of an evolutionary strategy with earlier PCI™ desktop/server mechanical and electrical specifications.
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Integrity & Data Encryption (IDE) provides confi...view moreIntegrity & Data Encryption (IDE) provides confidentiality, integrity, and replay protection for TLPs. It flexibly supports a variety of use models, while providing broad interoperability. The cryptographic mechanisms are aligned to current industry best practices and can be extended as security requirements evolve. The security model considers threats from physical attacks on Links, including cases where an adversary uses lab equipment, purpose-built interposers, malicious Extension Devices, etc. to examine data intended to be confidential, modify TLP contents, & reorder and/or delete TLPs. TLP traffic can be secured as it transits Switches, extending the security model to address threats from reprogramming Switch routing mechanisms or using “malicious” Switches. Compared to the Member Review copy, and consistent with the “NOTICE TO REVIEWERS” in that copy, this final revision contains significant revisions to the key management protocol in order to align it closely with the DMTF’s Secured Messages using SPDM Specification, which was not available at the time the Member Review copy was prepared. Additionally, the final copy includes significant improvements in protection against Adversary-in-the-Middle attacks, and, consistent with member feedback received in response to the query regarding key size for AES-GCM applied to IDE TLPs, supports only the 256b key size.
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Loosens restrictions on use of PASID to allow PASID ...view moreLoosens restrictions on use of PASID to allow PASID to be applied to Memory Requests using Translated addresses (AT=Translated).
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This ECN defines a new Request, the Deferrable Memor...view moreThis ECN defines a new Request, the Deferrable Memory Write (DMWr), that requires the Completer to return an acknowledgement to the Requester, and provides a mechanism for the recipient to defer (temporarily refuse to service) the Request.
To provide space for the required control registers, this ECN also defines an Extended Capability, the Device 3 Extended Capability, to provide Device Capabilities 3, Device Control 3, and Device Status 3 registers. This Extended Capability is required for DMWr support, but can also be applied to other uses besides DMWr, and therefore can be implemented by Functions that do not support DMWr.
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This ECR defines an adaptation of the data objects a...view moreThis ECR defines an adaptation of the data objects and underlying protocol defined in the DMTF SPDM specification (https://www.dmtf.org/dsp/DSP0274) for PCIe components, providing a mechanism to verify the component configuration and firmware/executables (Measurement) and hardware identities (Authentication). “Firmware” in this context includes configuration settings in addition to executable code. This protocol can be operated via the Data Object Exchange (DOE) mechanism, or through other means, for example via MCTP messaging conveyed using PCIe Messages, or via SMBus, I2C, or other management I/O. Data Object Exchange (DOE) is defined in the Data Object Exchange ECN to the PCIe Base Specification Rev 4.0, 5.0, approved on 12 Mar 2020.
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This ECR defines an optional Extended Capability str...view moreThis ECR defines an optional Extended Capability structure and associated control mechanisms to provide System Firmware/Software the ability to perform data object exchanges with a Function or RCRB.
To support Component Measurement and Authentication (CMA) accessible in-band via host firmware/software, Data Object Exchange (DOE) is required, and CMA motivates the need for DOE, although broader uses are anticipated.
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Revision A (January 30, 2020) corrects an error in t...view moreRevision A (January 30, 2020) corrects an error in the original revision (September 29, 2019). The ATS Memory Attributes Supported field in the ATS Capabilities Register is now assigned bit location 8. It was previously assigned bit location 7. The affected text is highlighted in Table 10-9: ATS Capability Register.
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Shadow Functions are permitted to be assigned only w...view moreShadow Functions are permitted to be assigned only where currently unused Functions reside. The Function declaring the shadowing is permitted to overflow its Transaction ID space over into the Shadow Function. The impetus for defining Shadow Functions is to provide more Transaction ID space without increasing the Tag field, since there are no straightforward means to do that at the current time.
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Due to ambiguity in earlier versions of the PCIe Bas...view moreDue to ambiguity in earlier versions of the PCIe Base Specification two different interpretations of the byte positions in the PTM ResponseD Message Propagation Delay field have been implemented. This ECR defines mechanisms that new hardware can implement to support the adaptation to either of the interpretations.
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There are four informative ...view moreThere are four informative "changebar" versions of the PCI Express Base 5.0 Specification comparing Base 5.0/1.0 to Base 5.0/0.9 and comparing Base 4.0 and Base 5.0. HTML and PDF versions are provided. Both versions are derived from common source material but have different characteristics, and readers may wish to reference both. These documents are non-normative - the NCB PCI Express Base Specification Revision 5.0, Version 1.0 (NCB-PCI_Express_Base_5.0r1.0-2019-05-22.pdf) is the normative version of this specification.
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This specification describes the PCI Express archite...view moreThis specification describes the PCI Express architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
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