Specifications

Technology: PCI Conventional
Specification Title Spec Rev
Document Type Release Date
SHPC Memory Access Granularity
Restrict PCI Standard Hot-Plug (SHPC) device drivers...view more Restrict PCI Standard Hot-Plug (SHPC) device drivers to a memory access granularity of maximum one DWORD (aligned) when reading or writing to the SHPC memory space. show less
1.x ECN
SHPC Extensions for PCI-X 2.0
Changes are to the PCI Standard Hot-Plug Controller ...view more Changes are to the PCI Standard Hot-Plug Controller and Subsystem Specification, Revision 1.0. This ECN extends the Standard Hot-plug Controller Specification to support the additional PCI-X speeds and modes allowed by the PCI-X 2.0 specification. Specifically, this ECN provides the required hardware and software extensions needed to support the new PCI-X 2.0 speeds of 266 and 533 and also the software extensions needed to control PCI-X 2.0 mode ECC and parity operation. show less
1.x ECN
Interrupt Line Register Usage
This ECN is a request for modifications to the parag...view more This ECN is a request for modifications to the paragraphs describing the Interrupt Line Register usage for the PCI-to-PCI-Bridge. The purpose is to clarify the differences between the usages on PC-compatible systems and DIG64-compliant systems. show less
1.x ECN
Mini PCI Specification Revision 1.0
...view more The Mini PCI Specification defines an alternate implementation for small form factor PCI cards referred to in this specification as a Mini PCI Card. This specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Local Bus Specification. show less
1.x Specification
PCI Bus Power Management Interface Specification Revision 1.2
The goal of this specification is to establish a sta...view more The goal of this specification is to establish a standard set of PCI peripheral power management hardware interfaces and behavioral policies. Once established, this infrastructure enables an operating system to intelligently manage the power of PCI functions and buses. show less
1.x Specification
PCI Hot-Plug Specification Revision 1.1
...view more The primary objective of this specification is to enable higher availability of file and application servers by standardizing key aspects of the process of removing and installing PCI add-in cards while the system is running. Although these same principles can be applied to desktop and portable systems using PCI buses, the operations described here target server platforms. show less
1.x Specification
PCI Standard Hot-Plug Controller and Subsystem Specification Revision 1.0
The primary purpose of this document is to specify a...view more The primary purpose of this document is to specify a standard implementation of a PCI Hot-Plug Controller called the Standard Hot-Plug Controller (SHPC). show less
1.x Specification
PCI-to-PCI Bridge Architecture Specification Revision 1.2
This specification defines the behavior of a complia...view more This specification defines the behavior of a compliant PCI-to-PCI bridge. A PCI-to-PCI bridge that conforms to this specification and the PCI Local Bus Specification is a compliant implementation. Compliant bridges may differ from each other in performance and, to some extent, functionality. show less
1.x Specification
PCI-to-PCI Bridge Architecture Specification Revision 1.2 with Change Bar
This specification defines the behavior of a complia...view more This specification defines the behavior of a compliant PCI-to-PCI bridge. A PCI-to-PCI bridge that conforms to this specification and the PCI Local Bus Specification is a compliant implementation. Compliant bridges may differ from each other in performance and, to some extent, functionality. show less
1.x Specification
PCI/PCI-X Connector Contact Finish Changes
The intent of this ECR is to update the PCI base spe...view more The intent of this ECR is to update the PCI base specifications to include PCI connector metallurgical practices which have been commonly accepted or introduced since the original wording was drafted before the PCI 2.0 specification. With an overwhelming majority of PCI and PCI-X connectors shipped in the world that do not meet the PCI specification for contact finish plating, the most efficient way to rectify the situation is to correct the specification. show less
2.x ECN
MSI-X
Extend the current MSI functionality to support a la...view more Extend the current MSI functionality to support a larger number of MSI vectors, plus a separate and independent Message Address and Message Data for each MSI vector. Allow more flexibility when SW allocates fewer MSI vectors than requested by HW. Enable per-vector masking capability. show less
2.x ECN
Errata for PCI 2.3 2.x Errata
PCI Local Bus Specification Revision 2.3
This document contains the formal specifications of ...view more This document contains the formal specifications of the protocol, electrical, and mechanical features of the PCI Local Bus Specification, Revision 2.3, as the production version effective March 29, 2002. The PCI Local Bus Specification, Revision 2.2, issued December 18, 1998, is superseded by this specification. show less
2.x Specification
PCI Bios Specification Revision 2.1
This document describes the software interface prese...view more This document describes the software interface presented by the PCI BIOS functions. This interface provides a hardware independent method of managing PCI devices in a host computer. show less
2.x Specification
Enhanced Allocation (EA) for Memory and I/O Resources
Enhanced Allocation is an optional Conventional PCI ...view more Enhanced Allocation is an optional Conventional PCI Capability that may be implemented by Functions to indicate fixed (non reprogrammable) I/O and memory ranges assigned to the Function, as well as supporting new resource “type” definitions and future extensibility to also support reprogrammable allocations. show less
3.x ECN
Changing Class Code for InfiniBand Adapter
This ECN updates the subclass ID description in the ...view more This ECN updates the subclass ID description in the Class Code & Capability ID Specification. show less
3.x ECN
Class Code & Capability ID Extraction
This ECN extracts the Class Code definitions from Ap...view more This ECN extracts the Class Code definitions from Appendix D and the Capability ID definitions from Appendix H, for consolidation into a new standalone document that’s easier to maintain. The new document will also consolidate Extended Capability definitions from the PCIe Base spec and various other PCIe specs. show less
3.x ECN
Generic Capability Structure for SATA Host Bus Adapters
The functional changes proposed involve the definiti...view more The functional changes proposed involve the definition of a new Capabilities List ID (and associated Capability register set). This new Capabilities ID will identify to system firmware (BIOS/OROM), a Serial ATA (SATA) host bus adapter’s (HBA) support of optional features that may be defined in the particular SATA HBA specification (i.e. Advanced Host Controller Interface - AHCI). show less
3.x ECN
PCI/PCI-X Connector Contact Finish Changes
The intent of this ECR is to update the PCI base spe...view more The intent of this ECR is to update the PCI base specifications to include PCI connector metallurgical practices which have been commonly accepted or introduced since the original wording was drafted before the PCI 2.0 specification. With an overwhelming majority of PCI and PCI-X connectors shipped in the world that do not meet the PCI specification for contact finish plating, the most efficient way to rectify the situation is to correct the specification. show less
3.x ECN
SATA Class Code ECN
Create a new class code for SerialATA host-based ada...view more Create a new class code for SerialATA host-based adapters (HBAs) that can be identified by system software. The new class code will allow for system software to identify a controller as being attached to serial ATA devices and serial attached SCSI devices. This will help system software load drivers that may be specific to these interfaces. show less
3.x ECN
MSI-X
Extend the current MSI functionality to support a la...view more Extend the current MSI functionality to support a larger number of MSI vectors, plus a separate and independent Message Address and Message Data for each MSI vector. Allow more flexibility when SW allocates fewer MSI vectors than requested by HW. Enable per-vector masking capability. show less
3.x ECN
Advanced Capabilities for Conventional PCI
For conventional PCI devices integrated into a PCI E...view more For conventional PCI devices integrated into a PCI Express Root Complex, this defines an optional capability structure that includes selected advanced features originally defined for PCI Express. This capability is intended to be extensible in the future. For the initial definition, the Transactions Pending (TP) and Function Level Reset (FLR) are included. show less
3.x ECN
PCIe Hot Plug
This ECN affects the PCI Firmware Specification v3.1...view more This ECN affects the PCI Firmware Specification v3.1 and allows certain errors to be suppressed by platform if software stack ensured error containment. Also removes the implementation note in section 4.5.2.4 which is not representative of OS behavior. show less
3.x ECN
PCI_OSC Clarifications
This ECN attempts to make clarifications such that t...view more This ECN attempts to make clarifications such that the system firmware and multiple operating systems can have the same interpretation of the specification and work interoperably. show less
3.x ECN
Unoccupied Slot Power Hand-off State Clarification
This ECN allows the unoccupied slots' power to be of...view more This ECN allows the unoccupied slots' power to be off at hand-off, which is a reasonable implementation and many systems implement that way today. show less
3.x ECN
PCI Option ROM CLP
This ECN rectifies the differences between the DMTF ...view more This ECN rectifies the differences between the DMTF SM CLP Specification and its supporting documents with the current PCI Firmware 3.0 Specification. Also, it clarifies the supporting documents required for successfully implementing CLP in an X86 PCI FW 3.0 compatible option ROM. show less
3.x ECN
Ignore PCI Boot Configuration_DSM Function
This ECN adds a function to the _DSM Definitions for...view more This ECN adds a function to the _DSM Definitions for PCI to provide an indication to an operating system that it can ignore the PCI boot configuration setup by the firmware during system initialization. show less
3.x ECN
Update DMTF SM CLP Specification References
This update references to sections in the DMTF Serve...view more This update references to sections in the DMTF Server Management Command Line Protocol (SM CLP) Specification (DSP0214) to match the most recent version SM CLP Specification (v1.0.2). It also clarifies that the references to the DMTF SM CLP specification are referencing v1.0.2. and adds a reference to the DMTF SM CLP specification in section 1.2 Reference Documents. show less
3.x ECN
UEFI PCI Services Update
This is a request to update the UEFI PCI Services....view more This is a request to update the UEFI PCI Services. No functional changes. In the case of the UGA reference, UGA has been obsolete by the UEFI Specification and is replaced by the new GOP. show less
3.x ECN
ACPI Additions for ASPM, OBFF, LTR ECNs
A number of PCIe base specifications ECNs have been ...view more A number of PCIe base specifications ECNs have been approved that require software support. In some cases, platform firmware needs to know if the OS running supports certain features, or the OS needs to be able to request control of certain features from platform firmware. In other cases, the OS needs to know information about the platform that cannot be discovered through PCI enumeration, and ACPI must be used to supply the additional information. show less
3.x ECN
PCIe Device Labeling under Operating Systems
This ECR proposes a mechanism (new extension to _DSM...view more This ECR proposes a mechanism (new extension to _DSM) to make the device names/labels under Operating Systems deterministic. Currently, there is no well defined mechanism to consistently associate platform specific device names and instances of a device type under operating system. As a result, instance labels for specific device types under various operating systems (ex: ethx label for networking device instance under Linux OS) do not always map into the platform designated device labels. Additionally, the instance labels can change based on the system configuration. For example, under Linux operating systems, the “eth0” label does not necessarily map to the first embedded networking device as designed in a given platform. Depending on the hardware bus topology, current configuration including the number and type of networking adapters installed, the eth0 label assignment could change in a given platform. show less
3.x ECN
UEFI Related Updates
Update the references to the latest UEFI Specificati...view more Update the references to the latest UEFI Specification. Make clarifications in 5.1.2 that the pointers to the Device List, the Configuration Utility Code header and the DMTF CLP Entry Point are not applicable to the UEFI Option ROMs. show less
3.x ECN
ACPI Additions for FW Latency Optimizations
This ECR provides two additional ACPI DSM functions ...view more This ECR provides two additional ACPI DSM functions to inform OS about the possible time reduction opportunities: show less
3.x ECN
Errata for PCI 3.0 3.x Errata
PCI Local Bus Specification Revision 3.0
...view more This document contains the formal specifications of the protocol, electrical, and mechanical features of the PCI Local Bus Specification, Revision 3.0, as the production version effective February 3, 2004. The PCI Local Bus Specification, Revision 2.3, issued March 29, 2002, is not superseded by this specification. show less
3.x Specification
PCI Local Bus Specification Revision 3.0 with Change Bar
This document contains the formal specifications of ...view more This document contains the formal specifications of the protocol, electrical, and mechanical features of the PCI Local Bus Specification, Revision 3.0, as the production version effective February 3, 2004. The PCI Local Bus Specification, Revision 2.3, issued March 29, 2002, is not superseded by this specification. show less
3.x Specification
PCI Firmware Specification Revision 3.2
This document describes the hardware independent fir...view more This document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer. show less
3.x Specification
PCI Firmware Specification Revision 3.1
This document describes the hardware independent fir...view more This document describes the hardware independent firmware interface for managing PCI™, PCI-X, and PCI Express® systems in a host computer. show less
3.x Specification
PCI Firmware Specification Revision 3.0
This document describes the hardware independent fir...view more This document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer. show less
3.x Specification
Enabling Multiple Base Addresses per PCI Segment Group ECN
The changes affect the PCI Firmware Specification, R...view more The changes affect the PCI Firmware Specification, Revision 3.2 and enable the MCFG table format to allow for multiple memory mapped base address entries, instances of Table 4-3, per single PCI Segment Group. show less
3.x ECN
Downstream Port Containment Related Enhancements ECN
The changes effect the PCI Firmware Specification, R...view more The changes effect the PCI Firmware Specification, Revision 3.2 and will enable the Operating System to advertise its Downstream Port containment related capabilities to the firmware. It also enables the Operating System and the Firmware to negotiate ownership of Downstream Port Containment extended capability register block and collaboratively manage Downstream Port Containment events. show less
3.x ECN
_HPX and PCIe Completion Timeout related _OSC Enhancements ECN
Changes are requested to be made to Section 4.5.1, _...view more Changes are requested to be made to Section 4.5.1, _OSC Interface for PCI Host Bridge Devices and Section 4.5.2.4 Dependencies Between _OSC Control Bits. The changes will enable the Operating System to advertise if it is capable of support _HPX PCI Express Descriptor Setting Record (Type 3) to the firmware. It also enables the Operating System and the Firmware to negotiate ownership of the PCIe Completion Timeout registers. show less
3.x ECN
(Firmware WG) | PCI Firmware Specification Revision 3.3 (Clean)
This document describes the hardware independent fir...view more This document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer. show less
3.x Specification
(Firmware WG) | PCI Firmware Specification Revision 3.3 (Change Bar)
This document describes the hardware independent fir...view more This document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer. show less
3.x Specification
Technology: PCI Express
Specification Title Spec Rev
Document Type Release Date
PASID Translation
The Process Address Space ID (PASID) ECN to the Base...view more The Process Address Space ID (PASID) ECN to the Base PCI Express Specification defines the PASID TLP Prefix. This companion ECN is optional normative and defines PASID TLP Prefix usage rules for ATS and PRI. show less
1.x ECN
Process Address Space ID (PASID)
This optional normative ECN defines an End-End TLP P...view more This optional normative ECN defines an End-End TLP Prefix for conveying additional attributes associated with a request. The PASID TLP Prefix is an End-End TLP Prefix as defined in the PCI Express Base Specification. Routing elements that support End-End TLP Prefixes (i.e. have the End-End TLP Prefix Supported bit Set in the Device Capabilities 2 register) can correctly forward TLPs containing a PASID TLP Prefix. show less
1.x ECN
REF CLK Delayed from CLKREQ# Assertion
This ECR requests making a change to the CLKREQ# ass...view more This ECR requests making a change to the CLKREQ# asserted low to clock active timing when latency tolerance reporting is supported and enabled for the function. The change would be to allow this specified value to exceed 400ns up to a limit consistent with the latency value established by the Latency Tolerance Reporting (LTR) mechanism. show less
1.x ECN
Second Wireless Disable Pin
This ECN is for the functional addition of a second ...view more This ECN is for the functional addition of a second wireless disable signal (W_DISABLE2#) as a new definition of Pin 51 (Reserved). When this optional second wireless disable signal is not implemented by the system, the original intent of a single wireless disable signal disabling all radios on the add-in card when asserted is still required. show less
1.x ECN
SMBus interface for SSD Socket 2 and Socket 3
SMBus interface signals are included in sections 3.2...view more SMBus interface signals are included in sections 3.2 and 3.3 and related minor clarifications added to sections 1.2, 1.3, 2.2, 4.1, 4.2, 5.2.2, and 5.3. show less
1.x ECN
WWAN Key C Definition
This ECR describes the necessary changes to enable a...view more This ECR describes the necessary changes to enable a new WWAN Key C definition to be included as an addition to the existing spec. The intent is to create a dedicated WWAN socket Key and pinout definition. This new pinout definition will be focused on WWAN specific interfaces and needs.  show less
1.x ECN
M.2 2242 WWAN Module
Add 2242 form factor for WWAN modules using Socket 2...view more Add 2242 form factor for WWAN modules using Socket 2 with key B. show less
1.x ECN
M.2 Signal Definition – Audio & ANTCTL Functions
Definition of the four Audio pins to provide definit...view more Definition of the four Audio pins to provide definitive functions assigned to each pin of the Audio interface. show less
1.x ECN
Power-up requirements for PCIe side bands (PERST#, etc.)
Section 3.1.3.2.1 is redefined to provide a more rea...view more Section 3.1.3.2.1 is redefined to provide a more realistic timing model for reset. show less
1.x ECN
Tx Blanking and SYSCLK on Socket 1 Related Pinouts
The proposed change is to include 2 GNSS Aiding sign...view more The proposed change is to include 2 GNSS Aiding signals, that we already have allocated in the Type 1216 pinout, to the Socket 1 Key E pinout and Type 2226/3026 pinout. Due to lack of free pins in the Key E pinout, it is proposed to define 2 SDIO Input signals as dual functional pins. They would be defined with their original SDIO functionality along with and alternate GNSS Aiding signals functionality to enable a GNSS solution on Type 2230 solutions on Socket 1 Key E solutions. The GNSS signals to be added are the Tx Blanking and SYSCLK signals and it is suggested to overlay them on the SDIO RESET# and SDIO CLK respectively which are also inputs. In this way it is less likely to cause a potential contention.  show less
1.x ECN
M.2 COEX Signal Definition - UART
Definition of two of the three COEX pins as a UART T...view more Definition of two of the three COEX pins as a UART Tx/Rx communication path between Socket 1 and Socket 2 in favor of WWAN ßà Connectivity coexistence. The intent is to definitively define the location of the source and sink sides of the signal path.  show less
1.x ECN
Transition of NFC Signals from 3.3V to 1.8V
The proposed change is to change the current voltage...view more The proposed change is to change the current voltage level of the NFC related signals (I2C DATA, I2C CLK and ALERT#) on the Connectivity pinouts and definitions from 3.3V to 1.8V signal level to better align with future platforms operating signal levels typical in the industry.  show less
1.x ECN
Power-up requirements for PCIe side bands in a Vbat powered system
In ECN “Power-up requirements for PCIe side bands (P...view more In ECN “Power-up requirements for PCIe side bands (PERST#, etc.)” - submitted by Dave Landsman and Ramdas Kachare - section 3.1.3.2.1 is redefined to provide a more realistic timing model for reset. show less
1.x ECN
Address Translation Services 1.0 Specification Errata 1.x Errata
Errata for the PCI Express Base Specification Revision 1.1 1.x Errata
Address Translation Services Revision 1.1
This specification describes the extensions required...view more This specification describes the extensions required to allow PCI Express Devices to interact with an address translation agent (TA) in or above a Root Complex (RC) to enable translations of DMA addresses to be cached in the Device. The purpose of having an Address Translation Cache (ATC) in a Device is to minimize latency and to provide a scalable distributed caching solution that will improve I/O performance while alleviating TA resource pressure. This specification must be used in conjunction with the PCI Express Base Specification, Revision 1.1, and associated ECNs. show less
1.x Specification
Address Translation Services Revision 1.0
This specification describes the extensions required...view more This specification describes the extensions required to allow PCI Express Devices to interact with an address translation agent (TA) in or above a Root Complex (RC) to enable translations of DMA addresses to be cached in the Device. The purpose of having an Address Translation Cache (ATC) in a Device is to minimize latency and to provide a scalable distributed caching solution that will improve I/O performance while alleviating TA resource pressure. This specification must be used in conjunction with the PCI Express Base Specification, Revision 1.1, and associated ECNs. show less
1.x Specification
Single Root I/O Virtualization and Sharing Specification Revision 1.1 with Change Bar
The purpose of this document is to specify PCI™ I/O ...view more The purpose of this document is to specify PCI™ I/O virtualization and sharing technology. The specification is focused on single root topologies; e.g., a single computer that supports virtualization technology. show less
1.x Specification
Single Root I/O Virtualization and Sharing Specification Revision 1.1
The purpose of this document is to specify PCI™ I/O ...view more The purpose of this document is to specify PCI™ I/O virtualization and sharing technology. The specification is focused on single root topologies; e.g., a single computer that supports virtualization technology. show less
1.x Specification
Single Root I/O Virtualization and Sharing Specification Revision 1.0
The purpose of this document is to specify PCI™ I/O ...view more The purpose of this document is to specify PCI™ I/O virtualization and sharing technology. The specification is focused on single root topologies; e.g., a single computer that supports virtualization technology. show less
1.x Specification
Multi-Root I/O Virtualization and Sharing Specification Revision 1.0
The purpose of this document is to specify PCI® I/O ...view more The purpose of this document is to specify PCI® I/O virtualization and sharing technology. The specification is focused on multi-root topologies; e.g., a server blade enclosure that uses a PCI Express® Switch-based topology to connect server blades to PCI Express Devices or PCI Express to-PCI Bridges and enable the leaf Devices to be serially or simultaneously shared by one or more System Images (SI). Unlike the Single Root IOV environment, independent SI may execute on disparate processing components such as independent server blades. show less
1.x Specification
PCI Express M.2 Specification Revision 1.0
The M.2 form factor is used for Mobile Add-In cards....view more The M.2 form factor is used for Mobile Add-In cards. The M.2 is a natural transition from the Mini Card and Half-Mini Card to a smaller form factor in both size and volume. The M.2 is a family of form factors that will enable expansion, contraction, and higher integration of functions onto a single form factor module solution. show less
1.x Specification
PCI Express® 225 W/300 W High Power Card Electromechanical Specification Revision 1.0
The main objective of this specification is to suppo...view more The main objective of this specification is to support PCI Express® add-in cards that require higher power than specified in the PCI Express Card Electromechanical Specification and the PCI Express x16 Graphics 150W-ATX Specification. show less
1.x Specification
PCI Express Base Specification Revision 1.1
This specification describes the PCI Express archite...view more This specification describes the PCI Express architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express specification. show less
1.x Specification
PCI Express Base Specification Revision 1.1 with Change Bar
This specification describes the PCI Express archite...view more This specification describes the PCI Express architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express specification. show less
1.x Specification
PCI Express Card Electromechanical Specification Revision 1.1
This specification is a companion for the PCI Expres...view more This specification is a companion for the PCI Express Base Specification, Revision 1.1. Its primary focus is the implementation of an evolutionary strategy with the current PCI desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express Mini Card are covered in other separate specifications. show less
1.x Specification
PCI Express Card Electromechanical Specification Revision 1.1 with Change Bar
This specification is a companion for the PCI Expres...view more This specification is a companion for the PCI Express Base Specification, Revision 1.1. Its primary focus is the implementation of an evolutionary strategy with the current PCI desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express Mini Card are covered in other separate specifications. show less
1.x Specification
PCI Express Mini Card Electromechanical Specification Revision 1.2
This specification defines an implementation for sma...view more This specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 1.1. Where this specification does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs. show less
1.x Specification
PCI Express Mini Card Electromechanical Specification Revision 1.2 with Change Bar
This specification defines an implementation for sma...view more This specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 1.1. Where this specification does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs. show less
1.x Specification
PCI Express External Cabling Specification Revision 1.0
This is a companion specification to the PCI Express...view more This is a companion specification to the PCI Express Base Specification. Its primary focus is the implementation of cabled PCI Express®. The discussions are confined to copper cabling and their connector requirements to meet the PCI Express signaling needs at 2.5 GT/s. No assumptions are made regarding the implementation of PCI Express compliant Subsystems on either side of the cabled Link; e.g., PCI Express Card Electromechanical (CEM), ExpressCard™, ExpressModule™, PXI Express™, system board, or any other form factor. Such form factors are covered in other separate specifications. show less
1.x Specification
PCI Express ExpressModule Electromechanical Specification Revision 1.0
This document is a companion specification to the PC...view more This document is a companion specification to the PCI Express Base Specification. Its primary focus is the implementation of a modular I/O form factor that is focused on the needs of workstations and servers from mechanicals and electrical requirements. The discussions are confined to the modules and their chassis slots requirements. Other form factors are covered in other separate specifications. show less
1.x Specification
PCI Express x16 Graphics 150W-ATX Specification Revision 1.0
The objectives of this specification are Support for...view more The objectives of this specification are Support for PCI Express™ graphics add-in cards that are higher power than specified in the PCI Express Card Electromechanical Specification, Forward looking for future scalability, Allow evolution of the PC architecture including graphics, Upgradeability, and Enhanced end user experience. show less
1.x Specification
PCI Express to PCI/PCI-X Bridge Specification Revision 1.0
...view more This specification describes the PCI Express to PCI/PCI-X bridge (also referred to herein as PCI Express bridge) architecture, interface requirements, and the programming model. show less
1.x Specification
PCI Express Architecture Mobile Graphics Low-Power Addendum to the PCI Express Base Specification Revision 1.0
This addendum to the PCI Express Base 1.0a describes...view more This addendum to the PCI Express Base 1.0a describes a low power extension intended primarily to support the reduced power requirements of mobile platforms. Its scope is restricted to the electrical layer and corresponds to Section 4.3 of PCI Express Base 1.0a. show less
1.x Specification
PCI Express® OCuLink Specification Revision 1.0
This document is a companion Specification to the PC...view more This document is a companion Specification to the PCI Express Base Specification and other PCI Express® 2 documents listed in Section 1.1. The primary focus of the PCI Express OCuLink Specification is the implementation 3 of internal and external small form factor PCI Express® connectors and cables optimized for the client and mobile 4 market segments. This Specification discusses cabling and connector requirements to meet the 8.0 GT/s signaling 5 needs in the PCI Express Base Specification. 6 No assumptions are made regarding the implementation of PCI Express compliant components on either side of 7 the Link; such components are addressed in other PCI Express Specifications. show less
1.x Specification
Supporting PCIe and SATA BGA form factor for SSDs ECN
This ECN is intended to define a new form-factor and...view more This ECN is intended to define a new form-factor and electrical pinout to the M.2 family. This proposal will allow PCIe and SATA to be delivered using a BGA package, expanding the use of the PCIe and SATA protocols in small form-factor applications. The new BGA pinout content is based on the Socket 3 Key-M definitions. BGA pinout supports additional pins than defined for Socket-3, for soldered-down form-factors. show less
1.x ECN
Errata for the PCI Express® OCuLink Specification Revision 1.0 1.x Errata
PCI Express M.2 Specification Revision 1.1
The M.2 form factor is intended for Mobile Adapters....view more The M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini 3 Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in 4 both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and 5 higher integration of functions onto a single form factor module solution. show less
1.x Specification
PCI Express M.2 Specification Revision 1.1 with Change Bar
The M.2 form factor is intended for Mobile Adapters....view more The M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini 3 Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in 4 both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and 5 higher integration of functions onto a single form factor module solution. show less
1.x Specification
OCuLink Memory Map Change
This is a modification of the cable assembly memory ...view more This is a modification of the cable assembly memory map defined in OCuLink 1.0, Appendix A. The addresses for the data bytes contained within the external cable assembly's memory will be reorganized. In addition, some data in these fields are modified. show less
1.x ECN
OCuLink Server Change
Table 6-12 and Table 6-13 in Section 6.9 are modifie...view more Table 6-12 and Table 6-13 in Section 6.9 are modified to reflect connector requirements for server/datacenter segment. In addition, this proposal also reflects a clarification in the Introduction text, Section 1 to include the server/datacenter market segment. show less
1.x ECN
OCuLink Skew
A PCI Express Receiver is required to tolerate 6 ns ...view more A PCI Express Receiver is required to tolerate 6 ns of lane to lane skew when operating at 8.0 GT/s. The PCI Express OCuLink Specification allowed the cable assembly to consume the entire budget. The Transmitter and traces routing to the OCuLink connector need some of this budget. The PCI Express Card Electromechanical Specification Revision 3.0 assigns 1.6 ns to the total interconnect lane to lane skew budget. show less
1.x ECN
PCIe BGA SSD 11.5x13 ECN
This proposal adds a new 11.5 mm x 13 mm PCIe BGA SS...view more This proposal adds a new 11.5 mm x 13 mm PCIe BGA SSD form factor to the M.2 v1.1 specification.  show less
1.x ECN
Enable PCIe and USB 3.1 Gen1 on M.2 Card Key B ECN
M.2 Key B (WWAN) is modified to enable PCIe and USB ...view more M.2 Key B (WWAN) is modified to enable PCIe and USB 3.1 Gen1 signals to be simultaneously present on the connector. This enables support for a single SKU M.2 card that supports both PCIe and USB 3.1 Gen1. There are two implementation options enabled: 1. State #14 in the “Socket 2 Add-in Card Configuration Table” is re-defined to indicate an Add-in Card built to the PCI Express M.2 Specification, Revision 1.1 or later where both PCIe and USB 3.1 Gen1 are both present on the connector. The choice of Port Configuration is vendor defined. This enables the host to unambiguously determine that PCIe and USB 3.1 Gen1 are present on the connector. 2. States #4, 5, 6, 7 in the “Socket 2 Add-in Card Configuration Table” are re-defined to indicate that in addition to USB 3.1 Gen1, PCIe may be present on the connector. This definition was used by M.2 cards built to the PCI Express M.2 Specification, Revision 1.0 (USB 3.1 Gen1 on connector; PCIe is “no connect”). This definition is now also permitted to be used by M.2 cards built to PCI Express M.2 Specification, Revision 1.1 or later to indicate that PCIe and USB 3.1 Gen1 are both present on the connector. This allows GPIO port configurations to remain consistent with all other existing states. show less
1.x ECN
OCuLink CPRSNT# Notice ECN
The cable presence (CPRSNT#) signal was incompletely...view more The cable presence (CPRSNT#) signal was incompletely and inaccurately specified in the original OCuLink 1.0 specification. The definition for the logic levels of this signal contradicted the active low naming convention. The direction has multiple contradictions. show less
1.x ECN
OCuLink BP Type ECN (Change Bar)
The backplane type (BP Type) signal was incompletely...view more The backplane type (BP Type) signal was incompletely specified in the original OCuLink 1.0 specification. Table 2-2 now includes a Type of logic used for this signal. A definition is provided for the logic levels of this signal. show less
1.x ECN
OCuLink Wiring Chart ECN (Change Bar)
a....view more a. The connector and cable assembly pinout tables have been revised to show the complete OCuLink pinout assignments in all cases. b. The two left-most columns in the cable pinout tables have been combined for clarity. c. Due to the fact that the pinout tables span multiple pages, P1/P2 designations have been included in the appropriate column titles of the cable pinout tables to make it easier to follow which end of the cable is being addressed on each page in each table. show less
1.x ECN
Add a Second PCIe Lane to Type 1216 SDIO Based LGA Module ECN
The M.2 Type 1216 Land Grid Array (LGA) Connectivity...view more The M.2 Type 1216 Land Grid Array (LGA) Connectivity module is modified to add a second PCIe lane. Referring to Figure 99 on page 127 show less
1.x ECN
Additional Voltage Value for PWR_1 Rail V0.3 ECN
This proposal adds an additional voltage value to th...view more This proposal adds an additional voltage value to the PWR_1 rail in the PCIe BGA SSD 11.5x13 ECR. Table 3 of section 3.4 in the document “PCIe BGA SSD 11.5x13 ECR”, defines the PWR_1 signal as a 3.3V source. This is changed to now also include a 2.5V rail. show less
1.x ECN
OCuLink BP Type ECN (Clean)
The backplane type (BP Type) signal was incompletely...view more The backplane type (BP Type) signal was incompletely specified in the original OCuLink 1.0 specification. Table 2-2 now includes a Type of logic used for this signal. A definition is provided for the logic levels of this signal.  show less
1.x ECN
OCuLink Wiring Chart ECN (Clean)
a....view more a. The connector and cable assembly pinout tables have been revised to show the complete OCuLink pinout assignments in all cases. b. The two left-most columns in the cable pinout tables have been combined for clarity. c. Due to the fact that the pinout tables span multiple pages, P1/P2 designations have been included in the appropriate column titles of the cable pinout tables to make it easier to follow which end of the cable is being addressed on each page in each table.  show less
1.x ECN
OCuLink Performance Table Change Notice ECN
This is a modification of the connector/cable perfor...view more This is a modification of the connector/cable performance tables defined in OCuLink 1.0, Section 6.9 and updated by the OCuLink Server Change ECN. The tables are reorganized to make this section of OCuLink more functional to the end user. Some table entry values are changed. show less
1.x ECN
OCuLink Cable Spec ECN (Change Bar)
The IL/ fitted IL requirements have been clarified....view more The IL/ fitted IL requirements have been clarified. The language of this portion of the spec has been reworked to eliminate confusion and provide uniformity in the subsections included in the following document. show less
1.x ECN
OCuLink Cable Spec ECN (Clean)
The IL/ fitted IL requirements have been clarified....view more The IL/ fitted IL requirements have been clarified. The language of this portion of the spec has been reworked to eliminate confusion and provide uniformity in the subsections included in the following document. show less
1.x ECN
NCTF Ground Ball Definition for PCIe BGA SSD 11.5x13 ECN
This change notice redefines the outer most ring of ...view more This change notice redefines the outer most ring of ground pins in the 11.5x13 BGA ball map to be redundant ground pins that are non-critical to function (NCTF).NCTF is a new pin definition indicating that while the pins shall continue to be connected to host and device ground, they are redundant such that they allow for mechanical failure but not functional failure. show less
1.x ECN
OCuLink Power Appendices ECN
The ECN provides clarif...view more The ECN provides clarifications for requirements that affect both systems implementers and cable assembly suppliers. The revisions will save time and confusion for the implementation of the optional external OCuLink cables. show less
1.x ECN
OCuLink Port and Cable Aggregation ECN
The OCuLink workgroup has received feedback that the...view more The OCuLink workgroup has received feedback that the information included in the specification regarding cable/ Port aggregation was unclear, particularly with respect to sideband management. Wording in sections relating to cable/ Port aggregation and sideband management has been reworked to be clearer. show less
1.x ECN
OCuLink x4 Drawing ECN
Drawings and dimensions for the x4 form factor have ...view more Drawings and dimensions for the x4 form factor have been corrected and clarified. show less
1.x ECN
OCuLink Implementation ECN
Several dimensions included in Chapter 9 of the OCuL...view more Several dimensions included in Chapter 9 of the OCuLink 1.0 Specification are repeated from previous chapters. 7 Repeated dimensions have been removed and additional pointers have been added to direct users where to find 8 more information about various OCuLink implementations. show less
1.x ECN
1.8V Sideband, Power Loss Notification, USB 2.0, and Higher Power Support ECN
This ECN introduces multiple features for M.2 and af...view more This ECN introduces multiple features for M.2 and affects the PCIe M.2 Specification Revision 1.1 and the PCIe BGA SSD 11.5x13 ECN. show less
1.x ECN
PCI Express OCuLink Specification Revision 1.0a
DISCLAIMER: Table A-1, Bytes 0 to 1...view more DISCLAIMER: Table A-1, Bytes 0 to 127 (Lower Memory Fields), contained an error in the 1.0 Specification. Byte 0, Identifier, was 0Eh and has been changed to 1Ch.   show less
1.x Specification
PCI Code and ID Assignment Specifications
This specification contains the Class Code and Capab...view more This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. show less
1.x Specification
(OCuLink WG) | PCI Express OCuLink Specification Revision 1.1
This document is a companion specification to the PC...view more This document is a companion specification to the PCI Express Base Specification and other PCI Express® documents listed in Section 1.1. The primary focus of the PCI Express OCuLink Specification is the implementation of internal and external small form factor PCI Express connectors and cables. This form factor supports multiple market segments, from client, mobile, server, datacenter, and storage. This specification discusses cabling and connector requirements to meet the 8.0 GT/s signaling needs in the PCI Express Base Specification. show less
1.x Specification
1.8V sideband, Power Loss Notification, USB 2.0, and higher power support, Revision B
Revision B (July 22, 2020) corrects an errata in the...view more Revision B (July 22, 2020) corrects an errata in the original revision (November 28, 2018). PWRDIS timings were incorrectly specified as a maximum when they are meant to be specified as a minimum value. The affected portion is highlighted in Table 3-26 PWRDIS AC characteristics. show less
1.x ECN
PCI Code and ID Assignment Specification
This specification contains the Class Code and Capab...view more This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. It is intended that this document be used along with the PCI Express Base Specification Revision 5.0. show less
1.x Specification
Lane Margining Test Extensions ECN
...view more Expansion of example methods for lane margining testing to create different electrical link conditions for the two test runs. These changes apply to both Add-in Card and System testing. Adding a repeatability test option as proof that lane margining measurement is implemented.   show less
1.x ECN
PCI Express Base Specification Revision 6.0.1, Version 1.0
This specification describes the PCI Express® archit...view more This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. This document defines the “base” specification for the PCI Express architecture, including the electrical, protocol, platform architecture and programming interface elements required to design and build devices and systems. show less
1.x Specification
PCI Express Base Specification Revision 6.0.1, Version 1.0 (Change Bar Version)
This is a change bar version of the PCI Express Base...view more This is a change bar version of the PCI Express Base 6.0 Specification comparing Base 6.0/1.0 to Base 6.0.1/1.0 show less
1.x Specification
Add a Second PCIe Lane to Type 1216 SDIO Based LGA Module ECN (rename) 1.x ECN
Add a Second PCIe Lane to Type 1216 SDIO Based LGA Module ECN (rename) 1.x ECN
Enable PCIe and USB 3.1 Gen1 on M.2 Card Key B ECN (rename) 1.x ECN
M.2 SSIC Eye Limits Definition ECN (rename) 1.x ECN
Supporting PCIe and SATA BGA form factor for SSDs ECN (rename) 1.x ECN
ECN_TPH-ST_Revision_20200924.pdf 1.x ECN
Data Object Exchange (DOE), Revision 1.1
This ECR defines a revised and extended Data Object ...view more This ECR defines a revised and extended Data Object Exchange mechanism. This ECN builds 5 upon the content defined in the ECN that defined the original revision of Data Object Exchange, published 26 March 2020 (document date of 12 March 2020). show less
1.x ECN
PCI Code and ID Assignment Specification Revision 1.15
This specification contains the Class Code and Capab...view more This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. It is intended that this document be used along with the PCI Express Base Specification Revision 5.0. show less
1.x Specification
Unordered IO (UIO) ECN
Defines a new wire semantic and related capabilities...view more Defines a new wire semantic and related capabilities for addressing the limitations of the PCI/PCIe fabric-enforced ordering rules. Specifically:  Fabrics with multiple paths between a source and destination cannot be supported; posted Writes don’t match the semantics of other fabrics, in that the Requester doesn’t (directly) know if/when a write has actually completed; and writes flowing towards destinations with differing write performance can cause global stalls show less
1.x ECN
M.2-1A Add-in Card and Connector Amperage Improvement
This proposal introduces a new version of the M.2 co...view more This proposal introduces a new version of the M.2 connector with improved amperage per pin to 1A, and card outline changes with increased component area options. show less
1.x ECN
PCI Code and ID Assignment Revision 1.16
This specification contains the Class Code and Capab...view more This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. It is intended that this document be used along with the PCI Express Base Specification Revision 5.0. show less
1.x Specification
Optimized Buffer Flush/Fill
This ECR proposes to add a new mechanism for platfor...view more This ECR proposes to add a new mechanism for platform central resource (RC) power state information to be communicated to Devices. This mechanism enables Optimized Buffer Flush/Fill (OBFF) by allowing the platform to indicate optimal windows for device bus mastering & interrupt activity. Devices can use internal buffering to shape traffic to fit into these optimal windows, reducing platform power impact. show less
2.x ECN
ASPM Optionality
Prior to this ECN, all PCIe external Links were requ...view more Prior to this ECN, all PCIe external Links were required to support ASPM L0s. This ECN changes the Base Specification to permit ASPM L0s support to be optional unless the applicable formfactor specification explicitly requires it. show less
2.x ECN
TLP Prefix
Emerging usage model trends indicate a requirement f...view more Emerging usage model trends indicate a requirement for increase in header size fields to provide additional information than what can be accommodated in currently defined TLP header sizes. The TLP Prefix mechanism extends the header size by adding DWORDS to the front of headers that carry additional information. show less
2.x ECN
TLP Processing Hints
This optional normative ECR defines a mechanism by w...view more This optional normative ECR defines a mechanism by which a Requester can provide hints on a per transaction basis to facilitate optimized processing of transactions that target Memory Space. The architected mechanisms may be used to enable association of system processing resources (e.g. caches) with the processing of Requests from specific Functions or enable optimized system specific (e.g. system interconnect and Memory) processing of Requests. show less
2.x ECN
Extended Tag Enable Default
The change allows a Function to use Extended Tag fie...view more The change allows a Function to use Extended Tag fields (256 unique tag values) by default; this is done by allowing the Extended Tag Enable control field to be set by default. show less
2.x ECN
Latency Tolerance Reporting
This ECR proposes to add a new mechanism for Endpoin...view more This ECR proposes to add a new mechanism for Endpoints to report their service latency requirements for Memory Reads and Writes to the Root Complex such that central platform resources (such as main memory, RC internal interconnects, snoop resources, and other resources associated with the RC) can be power managed without impacting Endpoint functionality and performance. show less
2.x ECN
ID-Based Ordering
This ECN proposes to add a new ordering attribute wh...view more This ECN proposes to add a new ordering attribute which devices may optionally support to provide enhanced performance for certain types of workloads and traffic patterns. The new ordering attribute relaxes ordering requirements between unrelated traffic by comparing the Requester/Completer IDs of the associated TLPs. show less
2.x ECN
Dynamic Power Allocation
DPA (Dynamic Power Allocation) extends existing PCIe...view more DPA (Dynamic Power Allocation) extends existing PCIe device power management to provide active (D0) device power management substates for appropriate devices, while comprehending existing PCIe PM Capabilities including PCI-PM and Power Budgeting. show less
2.x ECN
Multicast
This optional normative ECN adds Multicast functiona...view more This optional normative ECN adds Multicast functionality to PCI Express by means of an Extended Capability structure for applicable Functions in Root Complexes, Switches, and components with Endpoints. The Capability structure defines how Multicast TLPs are identified and routed. It also provides means for checking and enforcing send permission with Function-level granularity. The ECN identifies Multicast errors and adds an MC Blocked TLP error to AER for reporting those errors. show less
2.x ECN
Internal Error Reporting
PCI Express (PCIe) defines error signaling and loggi...view more PCI Express (PCIe) defines error signaling and logging mechanisms for errors that occur on a PCIe interface and for errors that occur on behalf of transactions initiated on PCIe. It does not define error signaling and logging mechanisms for errors that occur within a component or are unrelated to a particular PCIe transaction. show less
2.x ECN
Atomic Operations
This optional normative ECN defines 3 new PCIe trans...view more This optional normative ECN defines 3 new PCIe transactions, each of which carries out a specific Atomic Operation (“AtomicOp”) on a target location in Memory Space. The 3 AtomicOps are FetchAdd (Fetch and Add), Swap (Unconditional Swap), and CAS (Compare and Swap). FetchAdd and Swap support operand sizes of 32 and 64 bits. CAS supports operand sizes of 32, 64, and 128 bits. show less
2.x ECN
Resizable BAR Capability
This optional ECN adds a capability for Functions wi...view more This optional ECN adds a capability for Functions with BARs to report various options for sizes of their memory mapped resources that will operate properly. Also added is an ability for software to program the size to configure the BAR to. show less
2.x ECN
Alternative Routing-ID Interpretation (ARI)
For virtualized and non-virtualized environments, a ...view more For virtualized and non-virtualized environments, a number of PCI-SIG member companies have requested that the current constraints on number of Functions allowed per multi-Function Device be increased to accommodate the needs of next generation I/O implementations. This ECR specifies a new method to interpret the Device Number and Function Number fields within Routing IDs, Requester IDs, and Completer IDs, thereby increasing the number of Functions that can be supported by a single Device. show less
2.x ECN
Add USB 3.0 to the Mini Card
Mobile broadband peak data rates continue to increas...view more Mobile broadband peak data rates continue to increase. With LTE category 5, USB 2.0 will not meet the performance requirements. LTE category 5 peak data rates are 320 Mbps downlink; 75 Mbps uplink. Most USB 2.0 implementations achieve a maximum of about 240 Mbps throughput. Looking longer term, the ITU has set a target of 1 Gbits/s for low mobility applications for IMT Advanced. show less
2.x ECN
Tighten Mini Card Power Rail Voltage Tolerance
Modify the Mini Card specification to tighten the po...view more Modify the Mini Card specification to tighten the power rail voltage tolerance. show less
2.x ECN
Combined Antenna Tuning/Coexistence Signal ECR
Modify the PCI Express Mini Card specification to de...view more Modify the PCI Express Mini Card specification to define a new interface for tunable antennas. Modify the PCI Express Mini Card specification to enable existing coexistence signals to operate simultaneously with new tuneable antenna control signals. show less
2.x ECN
CEM Support Power
 ECR covers proposed modification of Section 4.2 Pow...view more  ECR covers proposed modification of Section 4.2 Power Consumption within the CEM Specification version 2.0. show less
2.x ECN
System Board Eye Height Specification Update
This ECN modifies the system board transmitter path ...view more This ECN modifies the system board transmitter path requirements (VTXS and VTXS_d) at 5 GT/s. As a consequence the minimum requirements for the add-in card receiver path sensitivity at 5 GT/s are also updated. show less
2.x ECN
Errata for the PCI Express Base Specification Revision 2.1 2.x Errata
Errata for the PCI Express Base Specification Revision 2.0 2.x Errata
PCI Express Architecture Configuration Space Test Specification Revision 2.0a
This document primarily covers PCI Express testing o...view more This document primarily covers PCI Express testing of root complexes, switches, bridges, and endpoints for the standard configuration mechanisms, registers, and features in Chapter 7 of the PCI Express Base Specification, Revision 2.0. This specification does not describe the full set of PCI Express tests and assertions for these devices. show less
2.x Specification
PCI Express Architecture Configuration Space Test Specification Revision 2.0a with Change Bar
This document primarily covers PCI Express testing o...view more This document primarily covers PCI Express testing of root complexes, switches, bridges, and endpoints for the standard configuration mechanisms, registers, and features in Chapter 7 of the PCI Express Base Specification, Revision 2.0. This specification does not describe the full set of PCI Express tests and assertions for these devices. show less
2.x Specification
PCI Express Architecture PHY Test Specification Revision 2.0
This document provides test descriptions for PCI Exp...view more This document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building add-in cards or system boards to the PCI Express Card Electromechanical Specification, Revision 2.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.  show less
2.x Specification
PCI Express Architecture Configuration Space Test Specification Revision 2.0
This document primarily covers PCI Express testing o...view more This document primarily covers PCI Express testing of root complexes, switches, bridges, and endpoints for the standard configuration mechanisms, registers, and features in Chapter 7 of the PCI Express Base Specification, Revision 2.0. This specification does not describe the full set of PCI Express tests and assertions for these devices. show less
2.x Specification
PCI Express Architecture Link Layer Test Specification Revision 2.0
This test specification primarily covers testing of ...view more This test specification primarily covers testing of all PCI Express Port types for compliance with the link layer requirements in Chapter 3 of the PCI Express Base Specification. At this point, this specification does not describe the full set of PCI Express tests for all link layer requirements. Going forward, as the testing gets mature, it is expected that more tests may be added as deemed necessary. show less
2.x Specification
PCI Express Architecture Transaction Layer Test Specification Revision 2.0
This document contains a list of Test Assertions and...view more This document contains a list of Test Assertions and a set of Test Definitions pertaining to the Transaction Layer. Assertions are statements of spec requirements which are measured by the algorithm details as specified in the Test Definitions. “Basic Functional Tests” are Test Algorithms which perform basic tests for key elements of Transaction Layer device functionality. This document does not describe a full set of PCI Express tests and assertions and is in no way intended to measure products for full design validation. Tests described here should be viewed as tools to checkpoint the result of product validation – not as a replacement for that effort. show less
2.x Specification
PCI Express Base Specification Revision 2.1 with Change Bar
This specification describes the PCI Express® archit...view more This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. show less
2.x Specification
PCI Express Card Electromechanical Specification Revision 2.0 with Change Bar
This specification is a companion for the PCI Expres...view more This specification is a companion for the PCI Express Base Specification, Revision 2.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express® Mini Card are covered in other separate specifications. show less
2.x Specification
PCI Express Card Electromechanical Specification Revision 2.0
This specification is a companion for the PCI Expres...view more This specification is a companion for the PCI Express Base Specification, Revision 2.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express® Mini Card are covered in other separate specifications. show less
2.x Specification
PCI Express Mini Card Electromechanical Specification Revision 2.0 with Change Bar
This specification defines an implementation for sma...view more This specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 2.0. Where this specification does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs. show less
2.x Specification
PCI Express Mini Card Electromechanical Specification Revision 2.0
This specification defines an implementation for sma...view more This specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 2.0. Where this specification does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs. show less
2.x Specification
PCI Express Base Specification Revision 2.0
This specification describes the PCI Express® archit...view more This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. show less
2.x Specification
PCI Express External Cabling Specification Revision 2.0
This is a companion specification to the PCI Express...view more This is a companion specification to the PCI Express Base Specification. Its primary focus is the implementation of cabled PCI Express®. The discussions are confined to copper cabling and their connector requirements to meet the PCI Express signaling needs at 5.0 GT/s. No assumptions are made regarding the implementation of PCI Express compliant Subsystems on either side of the cabled Link; e.g., PCI Express Card Electromechanical (CEM), ExpressCard5 ™, ExpressModule™, PXI Express™, system board, or any other form factor. Such form factors are covered in other separate specifications. show less
2.x Specification
PCI Express External Cabling Specification Revision 2.0 with Change Bar
This is a companion specification to the PCI Express...view more This is a companion specification to the PCI Express Base Specification. Its primary focus is the implementation of cabled PCI Express®. The discussions are confined to copper cabling and their connector requirements to meet the PCI Express signaling needs at 5.0 GT/s. No assumptions are made regarding the implementation of PCI Express compliant Subsystems on either side of the cabled Link; e.g., PCI Express Card Electromechanical (CEM), ExpressCard5 ™, ExpressModule™, PXI Express™, system board, or any other form factor. Such form factors are covered in other separate specifications. show less
2.x Specification
PCI Express Base Specification Revision 2.1
This specification describes the PCI Express® archit...view more This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. show less
2.x Specification
PCI Express® Mini Card Electromechanical Specification Revision 2.1
This specification defines an implementation for sma...view more This specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified subset of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 2.0. Where this specification 5 does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs. show less
2.x Specification
PCI Express® Mini Card Electromechanical Specification Revision 2.1 with Change Bar
This specification defines an implementation for sma...view more This specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified subset of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 2.0. Where this specification 5 does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs. show less
2.x Specification
(M.2 WG) | 1.8V sideband, Power Loss Notification, USB 2.0, and higher power support, Revision B 2.x ECN
NCTF Ground Ball Definition for PCIe BGA SSD 11.5x13 ECN (rename) 2.x ECN
PCIe BGA SSD 11.5x13 ECN (rename) 2.x ECN
Extension Devices
Provide specification for Physical Layer protocol aw...view more Provide specification for Physical Layer protocol aware Retimers for PCI Express 3.0/3.1. show less
3.x ECN
Separate Refclk Independent SSC Architecture (SRIS) JTOL and SSC Profile Requirements
Modifies specifications to provide revised JTOL curv...view more Modifies specifications to provide revised JTOL curve for SRIS mode and provides additional frequency domain constraint of SSC profile jitter on reference clocks. show less
3.x ECN
NOP DLLP
This ECN accomplishes two housekeeping tasks associa...view more This ECN accomplishes two housekeeping tasks associated with DLLP encoding. show less
3.x ECN
Readiness Notifications (RN)
 Defines mechanisms to reduce the time software need...view more  Defines mechanisms to reduce the time software needs to wait before issuing a Configuration Request to a PCIe Function or RC-integrated PCI Function following power on, reset, or power state transitions. show less
3.x ECN
M-PCIe
This ECR defines a new logical layer mapping of PCI ...view more This ECR defines a new logical layer mapping of PCI Express over the MIPI Alliance M-PHY1 specification. show less
3.x ECN
L1 PM Substates with CLKREQ, Revision 1.0a
 This ECR defines an optional mechanism, that establ...view more  This ECR defines an optional mechanism, that establishes, depending on implementation, one or more substates of the L1 Link state, which allow for dramatically lower idle power, including near complete removal of power for high speed circuits. show less
3.x ECN
Precision Time Measurement (PTM), Revision 1.0a
Defines an optional-normative Precision Time Measure...view more Defines an optional-normative Precision Time Measurement (PTM) capability. To accomplish this, Precision Time Measurement defines a new protocol of timing measurement/synchronization messages and a new capability structure. show less
3.x ECN
Separate Refclk Independent SSC Architecture (SRIS)
Provide specifications to enable separate Refclk wit...view more Provide specifications to enable separate Refclk with Independent Spread Spectrum Clocking (SSC) architecture. show less
3.x ECN
Change Root Complex Event Collector Class Code
Change the Sub-Class assignment for Root Complex Eve...view more Change the Sub-Class assignment for Root Complex Event Collector from 06h to 07h. show less
3.x ECN
Enhanced DPC (eDPC)
This optional normative ECN defines enhancements to ...view more This optional normative ECN defines enhancements to the Downstream Port Containment (DPC) ECN, an ECN that enabled automatic disabling of the Link below a Downstream Port following an uncorrectable error. The DPC ECN defined functionality for both Switch Downstream Ports and Root Ports. This ECN mostly defines functionality that is specific to Root Ports, functionality referred to as “RP Extensions for DPC”. show less
3.x ECN
Downstream Port Containment (DPC)
This ECN defines a new error containment mechanism f...view more This ECN defines a new error containment mechanism for Downstream Ports as well as minor enhancements that improve asynchronous card removal. Downstream Port Containment (DPC) is the automatic disabling of the Link below a Downstream Port following an uncorrectable error. This prevents the potential spread of data corruption (all TLPs subsequent to the error are prevented from propagating either Upstream or Downstream) and enables error recovery if supported by software. show less
3.x ECN
Lightweight Notification (LN) Protocol
This optional normative ECN defines a simple protoco...view more This optional normative ECN defines a simple protocol where a device can register interest in one or more cachelines in host memory, and later be notified via a hardware mechanism when any registered cachelines are updated. show less
3.x ECN
8.0 GT/s Receiver Impedance
Receivers that operate at 8.0 GT/s with an impedance...view more Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the following LTSSM states: Polling, Rx_L0s, L1, L2, and Disabled. show less
3.x ECN
End-End TLP Prefix Changes for RCs
 This change allows for all Root Ports with the End-...view more  This change allows for all Root Ports with the End-End TLP Prefix Supported bit Set to have different values for the Max End-End TLP Prefixes field in the Device Capabilities 2 register. It also changes and clarifies error handling for a Root Port receiving a TLP with more End-End TLP Prefixes than it supports. show less
3.x ECN
PLL Bandwidth Test Limits
Modifies the limits used by the PLL bandwidth test t...view more Modifies the limits used by the PLL bandwidth test to allow guardband for a single PLL test solution to be used at PCI-SIG compliance workshops without impacting pass/fail results for member companies. show less
3.x ECN
Protocol Multiplexing
This involves a minor upward compatible change in Ch...view more This involves a minor upward compatible change in Chapter 3, Chapter 4 and a new Appendix T. show less
3.x ECN
Errata for the PCI Express Base Specification Revision 3.0 3.x Errata
PCI Express Base Specification Revision 3.1a with Change Bar
This specification describes the PCI Express® archit...view more This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.  show less
3.x Specification
PCI Express Base Specification Revision 3.1a
This specification describes the PCI Express® archit...view more This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.  show less
3.x Specification
PCI Express Base Specification Revision 3.0 with Change Bar
This specification describes the PCI Express® archit...view more This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. show less
3.x Specification
PCI Express Base Specification Revision 3.0
This specification describes the PCI Express® archit...view more This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. show less
3.x Specification
PCI Express Card Electromechanical Specification Revision 3.0
This specification is a companion for the PCI Expres...view more This specification is a companion for the PCI Express Base Specification, Revision 3.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications. Access Test Channel S-Parameters. show less
3.x Specification
PCI Express Architecture PHY Test Specification Revision 3.0
This document provides test descriptions for PCI Exp...view more This document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building add-in cards or system boards to the PCI Express Card Electromechanical Specification 3.0. This specification does not describe the full set of PCI Express tests and assertions for these devices. show less
3.x Specification
PCI Express Architecture Configuration Space Test Specification Revision 3.0
This document primarily covers PCI Express testing o...view more This document primarily covers PCI Express testing of all defined PCI Express Device Types and RCRBs for the standard Configuration Space mechanisms, registers, and features in Chapter 6 of the PCI Local Bus Specification and Chapter 7 of the PCI Express Base Specification (some additional tested registers are described in other specifications that are referenced in the individual test description). show less
3.x Specification
PCI Express® Architecture Link Layer and Transaction Layer Test Specification Revision 3.0
This test specification primarily covers testing of ...view more This test specification primarily covers testing of PCI Express Device and Port types for compliance with the link layer and transaction layer requirements of the PCI Express Base Specification. Device and Port types that do not have a link (e.g., Root Complex Integrated Endpoints, Root Complex Event Collectors) are not tested under this test specification. At this point, this test specification does not describe the full set of PCI Express tests for all link layer or transaction layer requirements. show less
3.x Specification
PCI Express Architecture Platform Init/Config Revision 3.0
This test specification primarily covers tests of PC...view more This test specification primarily covers tests of PCI Express platform firmware for features critical to PCI Express. This specification does not include the complete set of tests for a PCI Express System. show less
3.x Specification
Seasim Software Package
The PCI Express 3.0 describes a method to simulate 8...view more The PCI Express 3.0 describes a method to simulate 8GT/s channel compliance using a statistical data eye simulator. To help members perform this simulation, a free open source tool called Seasim is provided below. This tool has been tested by members of the Electrical Working Group on multiple channels and has reached version 0.54 which should be useful for members designing 8GT/s systems.   show less
3.x Specification
Designated Vendor-Specific Extended Capability ECN
Define a Vendor-Specific Extended Capability that is...view more Define a Vendor-Specific Extended Capability that is not tied to the Vendor ID of the Component 5 or Function. This capability includes a Vendor ID that determines the interpretation of the remainder of the capability. It is otherwise similar to the existing Vendor-Specific Extended Capability. show less
3.x ECN
Emergency Power Reduction Mechanism with PWRBRK Signal ECN
This ECN defines two sets of related changes to supp...view more This ECN defines two sets of related changes to support an Emergency Power Reduction mechanism and to provide software visibility for this mechanism: 1. The Card Electromechanical Specification is updated to define an optional Emergency Power Reduction mechanism using RSVD pin B30. 2. The PCI Express Base Specification is updated to define an optional mechanism to indicate support for Emergency Power Reduction and to provide visibility as to the power reduction status of a Device. show less
3.x ECN
Root Complex Integrated Endpoints and IOV Updates
This ECN implements a variety of spec modifications ...view more This ECN implements a variety of spec modifications intended to correct inconsistencies related to, and to support more consistent implementation of, Root Complex integrated Endpoints, with a particular focus on issues relating to Single Root IO Virtualization (SR-IOV). show less
3.x ECN
M.2 SSIC Eye Limits Definition ECN
Definition of electrical eye limits (Eye Height and ...view more Definition of electrical eye limits (Eye Height and Eye Width) at the M.2 connector for SSIC host and device transmitter is proposed to be added in the specification. show less
3.x ECN
Expanded Resizable BARs ECN
The Resizable BAR capability currently allows BARs o...view more The Resizable BAR capability currently allows BARs of up to 512 GB (239), which allows address bits <38:0> to be passed into an Endpoint. This proposal extends resizable BARs to up to 263 bits, which supports the entire address space. show less
3.x ECN
Extended Message Data for MSI ECN
MSI is enhanced to include an Extended Message Data ...view more MSI is enhanced to include an Extended Message Data Field for the function generating the interrupt. The MSI Capability Structure is modified to enable the new feature to be enabled/disabled; and a new Extended Message Data Field to be configured. This change only applies to MSI and not MSI-X. show less
3.x ECN
SR-IOV Table Updates ECN
Update SR-IOV specification to reflect current PCI C...view more Update SR-IOV specification to reflect current PCI Code and ID Assignment Specification, regarding PCI capabilities and PCI-E extended capabilities. Clarify the requirements for VFs regarding the other Capabilities added by ECNs that should have updated the SR-IOV specification but did not. show less
3.x ECN
VF Resizable BARs ECN
Similar to, and based on, the Resizable BAR and Expa...view more Similar to, and based on, the Resizable BAR and Expanded Resizable BAR ECNs, this optional ECN adds a capability for PFs to be able to resize their VF BARs. This ECN is written with the expectation that the Expanded Resizable BAR ECN will have been released prior to this ECN’s release. This ECN supports all of the BAR sizes defined by both the Resizable BAR and Expanded Resizable BAR ECNs. show less
3.x ECN
Flattening Portal Bridge (FPB) ECN
This ECR is intended to address a class of issues wi...view more This ECR is intended to address a class of issues with PCI/PCIe architecture that relate to resource allocation inefficiency. To explain this, first we must define some terms: Static use cases, refer to scenarios where resources are allocated at system boot and then typically not changed again Dynamic use cases, refer to scenarios where run-time resource rebalancing (allocation of new resources, freeing of resources no longer needed) is required, due to hot add/remove, or by other needs. In the Static cases there are limits on the size of hierarchies and number of Endpoints due to the Bus & Device Number “waste” caused by the PCI/PCIe architectural definition for Switches, and by the requirement that Downstream Ports associate an entire Bus Number with their Link. This proposal addresses this class of problems by “flattening” the use of Routing IDs so that Switches and Downstream Ports are able to make more efficient use of the available space. show less
3.x ECN
Hierarchy ID Message ECN
Defines a new, optional PCI-SIG Defined Type 1 Vendo...view more Defines a new, optional PCI-SIG Defined Type 1 Vendor Defined Message. This message provides software and/or firmware, running on a Function, additional information to uniquely identify that Function, within a large system or a collection of systems. When a single system contains multiple PCI Express Hierarchies, this message tells a Function which Hierarchy it resides in. This value, in conjunction with the Routing ID number uniquely identifies a Function within that system. In clustered system, this message can include a System Globally Unique Identifier (System GUID) for each system. This value, in conjunction with the Hierarchy ID and Routing ID uniquely identifies a Function within that cluster. show less
3.x ECN
PCIe CEM Thermal Reporting ECN
This ECN specifies changes to the PCI Local Bus Spec...view more This ECN specifies changes to the PCI Local Bus Specification Revision 3.0 and the PCI Express CEM Specification 3.0. Changes to the PCI Local Bus Specification cover a new VPD encoding and a 32-bit field. Changes to the PCI Express CEM Specification cover a series of graphs used to classify air flow impedance and thermal properties under varying conditions as well as the test figure and process to create these graphs for a given adapter add-in card. Adapter add-in card types supported by this include all SINGLE-SLOT and DUAL-SLOT PCIe CEM adapter add-in cards without integrated air movers, including standard height adapter add-in cards as well as low-profile adapter add-in cards). Adapter add-in cards with an integrated air mover were not addressed due to the added complication of their integrated air mover in the overall platform’s potential cooling redundancy. show less
3.x ECN
Native PCIe Enclosure Management ECN
Defines mechanisms for simple storage enclosure mana...view more Defines mechanisms for simple storage enclosure management for NVMe SSDs, consistent with established capabilities in the storage ecosystem, with the first version of this capability defining a register interface for LED control. This ECN defines a new PCI Express extended capability called Native PCIe Enclosure Management (NPEM). show less
3.x ECN
_DSM Additions for Runtime Device Power Management
This ECN adds two capabilities by way of adding func...view more This ECN adds two capabilities by way of adding functions to the PCI Firmware Spec defined _DSM definition. show less
3.x ECN
Errata for the PCI Express® Base Specification Revision 3.1, Single Root I/O Virtualization and Sharing Revision 1.1, Address Translation and Sharing Revision 1.1, and M.2 Specification Revision 1.0
Final Release against Base Revision 3.1a.Subsequent ...view more Final Release against Base Revision 3.1a.Subsequent Errata will be against Base Revision 4.0 show less
3.x Errata
PCI Express SFF-8639 Module Specification, Revision 3.0, Version 1.0
The focus of this specification is on PCI Express (P...view more The focus of this specification is on PCI Express (PCIe®) solutions utilizing the SFF-8639 connector interface. Form factors include, but are not limited to, those described in the SFF-8201 Form Factor Drive Dimensions Specification. Other form factors, such as PCI Express CEM are documented in other independent specifications. show less
3.x Specification
SFF Manufacturing Mode ECN
High Volume Manufacturing (HVM) benefits from the ab...view more High Volume Manufacturing (HVM) benefits from the ability to set manufacturing specific SFF8639 Module modes that enable multiplexing of standard connector pins for manufacturing test specific use. This ECR is to define a method to allow the Host to enable Manufacturing Mode on the SFF-8639 Module through the standard interface connector. The Manufacturing Mode solution proposed is consistent with that already approved in SNIA SFFTA-1001 Revision 1.1 for SFF-8639 use. show less
3.x ECN
PCI Firmware Specification Revision 3.2
This document describes the hardware independent fir...view more This document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express systems in a host computer. show less
3.x Specification
_HPX and PCIe Completion Timeout related _OSC Enhancements ECN
Changes are requested to be made to Section 4.5.1, _...view more Changes are requested to be made to Section 4.5.1, _OSC Interface for PCI Host Bridge Devices and Section 4.5.2.4 Dependencies Between _OSC Control Bits. The changes will enable the Operating System to advertise if it is capable of support _HPX PCI Express Descriptor Setting Record (Type 3) to the firmware. It also enables the Operating System and the Firmware to negotiate ownership of the PCIe Completion Timeout registers. show less
3.x ECN
Downstream Port Containment Related Enhancements ECN
The changes effect the PCI Firmware Specification, R...view more The changes effect the PCI Firmware Specification, Revision 3.2 and will enable the Operating System to advertise its Downstream Port containment related capabilities to the firmware. It also enables the Operating System and the Firmware to negotiate ownership of Downstream Port Containment extended capability register block and collaboratively manage Downstream Port Containment events. show less
3.x ECN
Enabling Multiple Base Addresses per PCI Segment Group ECN
The changes affect the PCI Firmware Specification, R...view more The changes affect the PCI Firmware Specification, Revision 3.2 and enable the MCFG table format to allow for multiple memory mapped base address entries, instances of Table 4-3, per single PCI Segment Group. show less
3.x ECN
OCuLink Memory Map Correction ECN (Clean)
This is a modification of the cable assembly memory ...view more This is a modification of the cable assembly memory map defined in the OCuLink Memory Map ECN. Some bits contained within the external cable assembly's memory are modified to allow for cable aggregation. show less
3.x ECN
OCuLink Memory Map Correction ECN (Change Bar)
This is a modification of the cable assembly memory ...view more This is a modification of the cable assembly memory map defined in the OCuLink Memory Map ECN. Some bits contained within the external cable assembly's memory are modified to allow for cable aggregation. show less
3.x ECN
PCI Express M.2 8GT/s Compliance ECN
This proposal introduces 8GT/s electrical compliance...view more This proposal introduces 8GT/s electrical compliance details for M.2 based SSDs.  show less
3.x ECN
Voltage Indication for PCIe BGA SSD 16x20 ECN
This proposal repurposes five RFU pins in the 16 mm ...view more This proposal repurposes five RFU pins in the 16 mm x 20 mm BGA ball map to be optionally used for indicating PWR1, PWR2, and PWR3 supply voltage requirements to the Platform.  show less
3.x ECN
PCI Express M.2™ Specification Revision 3.0, Version 1.2
The M.2 form factor is intended for Mobile Adapters....view more The M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution. show less
3.x Specification
PCI Firmware Specification Revision 3.0
This document describes the hardware independent fir...view more This document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer. show less
3.x Specification
Ignore PCI Boot Configuration_DSM Function
This ECN adds a function to the _DSM Definitions for...view more This ECN adds a function to the _DSM Definitions for PCI to provide an indication to an operating system that it can ignore the PCI boot configuration setup by the firmware during system initialization.  show less
3.x ECN
PCI_OSC Clarifications
This ECN attempts to make clarifications such that t...view more This ECN attempts to make clarifications such that the system firmware and multiple operating systems can have the same interpretation of the specification and work interoperably. show less
3.x ECN
PCI Option ROM CLP
This ECN rectifies the differences between the DMTF ...view more This ECN rectifies the differences between the DMTF SM CLP Specification and its supporting documents with the current PCI Firmware 3.0 Specification. Also, it clarifies the supporting documents required for successfully implementing CLP in an X86 PCI FW 3.0 compatible option ROM. show less
3.x ECN
ACPI Additions for ASPM, OBFF, LTR ECNs
A number of PCIe base specifications ECNs have been ...view more A number of PCIe base specifications ECNs have been approved that require software support. In some cases, platform firmware needs to know if the OS running supports certain features, or the OS needs to be able to request control of certain features from platform firmware. In other cases, the OS needs to know information about the platform that cannot be discovered through PCI enumeration, and ACPI must be used to supply the additional information.  show less
3.x ECN
PCI Firmware Specification Revision 3.1
This document describes the hardware independent fir...view more This document describes the hardware independent firmware interface for managing PCI™, PCI-X, and PCI Express® systems in a host computer. show less
3.x Specification
PCIe Hot Plug
This ECN affects the PCI Firmware Specification v3.1...view more This ECN affects the PCI Firmware Specification v3.1 and allows certain errors to be suppressed by platform if software stack ensured error containment. Also removes the implementation note in section 4.5.2.4 which is not representative of OS behavior. show less
3.x ECN
PCI Express External Cabling Specification Revision 3.0, Version 1.0
This is a companion specification to the PCI Exp...view more This is a companion specification to the PCI Express Base Specification. The primary focus of this specification is the implementation of cabled PCI Express®. No assumptions are made regarding the implementation of PCI Express-compliant Subsystems on either side of the cabled Link (PCI Express Card Electromechanical (CEM), ExpressCard™, ExpressModule™, PXI Express™, or any other form factor). Such form factors are covered in separate specifications. show less
3.x Specification
1.8V Sideband, Power Loss Notification, USB 2.0, and Higher Power Support ECN, Revision A
Revision A (March 4, 2020) corrects an oversight in ...view more Revision A (March 4, 2020) corrects an oversight in the original revision (November 28, 2018). The Socket 2 Key B PCIe/USB3.1 Gen1-based WWAN Adapter Pinout was not updated to reflect the addition of 1.8V sideband support like the other tables. The affected portion is highlighted in Table 33 Socket 2 Key B PCIe/USB3.1 Gen1-based WWAN Adapter Pinout. show less
3.x ECN
High Power M.2 Heat Spreader ECN
This proposal introduces an additional width, compon...view more This proposal introduces an additional width, component heights, and the ability to specify the top surface as a planar. show less
3.x ECN
PCI Express External Cabling Specification Revision 3.0a (Clean)
This is a companion specification to the PCI Express...view more This is a companion specification to the PCI Express Base Specification. The primary focus of this specification is the implementation of cabled PCI Express®. No assumptions are made regarding the implementation of PCI Express-compliant Subsystems on either side of the cabled Link (PCI Express Card Electromechanical (CEM), ExpressCard™, ExpressModule™, PXI Express™, or any other form factor). Such form factors are covered in separate specifications show less
3.x Specification
(M.2 WG) | M.2 Socket-1 Enhancements ECN
...view more The changes are to Socket-1, Keys E and A-E Addition of 1.8V IO support type (1 pin) Addition of 1.8V IO Voltage source (1 pin) Addition of WI-FI_DISABLE and BT_DISABLE signals overlaid onto W_DISABLE1#, W_DISABLE2# Additional antenna assignment which allows for multiple Bluetooth antennas. show less
3.x ECN
(M.2 WG) | Add Core Voltage 0.8 V in PWR_3 for BGA SSD ECN
Add core voltages 0.8 V in PWR_3....view more Add core voltages 0.8 V in PWR_3. II. Add new pin configuration including 0.8 V. show less
3.x ECN
(Firmware WG) | PCI Firmware Specification Revision 3.3 (Clean)
This document describes the hardware independent fir...view more This document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer. show less
3.x Specification
(Firmware WG) | PCI Firmware Specification Revision 3.3 (Change Bar)
This document describes the hardware independent fir...view more This document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer. show less
3.x Specification
PCI Express M.2 Specification Revision 3.0, Version 1.2 (Clean) 3.x Specification
PCI Express M.2 Specification Revision 3.0, Version 1.2 (Change Bar) 3.x Specification
Additional voltage value for PWR_1 rail V0.3 ECN (rename) 3.x ECN
Errata for the PCI Express Base Specification Revision 3.1, Single Root IO Virtualization and Sharing Revision 1.1, Address Translation and Sharing Revision 1.1, and M.2 Specification Revision 1.0 (rename) 3.x Errata
Expansion ROM Validation ECN
Provide an optional mechanism to indicate to softwar...view more Provide an optional mechanism to indicate to software the results of a hardware validation of Expansion ROM contents. show less
4.x ECN
PCI Express® Base Specification Revision 4.0, Version 1.0
This specification describes the PCI Express® archit...view more This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. show less
4.x Specification
PCI Express® Base Specification Revision 4.0, Version 1.0 (Change Bar)
This specification describes the PCI Express® archit...view more This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. show less
4.x Specification
PCIe Link Activation ECN
Link Activation allows software to temporarily disab...view more Link Activation allows software to temporarily disable Link power management, enabling the avoidance of the architecturally mandated stall for software-initiated L1 Substate exits. show less
4.x ECN
Address Translation Relaxed Ordering ECN
This ECN allows Address Translation Requests and Com...view more This ECN allows Address Translation Requests and Completions to support the Relaxed Ordering bit, where are currently defined to be Reserved for these types of TLPs. The proposal preserves interoperability with older Translation Agents. show less
4.x ECN
Root Complex Event Collector Bus Number Association ECN
This ECN enhances Root Complex Event Collectors (RCE...view more This ECN enhances Root Complex Event Collectors (RCECs) to allow them to be associated with Devices located on additional Bus numbers. show less
4.x ECN
Errata for the PCI Express® Base Specification Revision 4.0 4.x Errata
Async Hot-Plug Updates ECN
This ECN updates several areas related to hot-plug f...view more This ECN updates several areas related to hot-plug functionality, mostly related to Async hot-plug, which is now growing in importance due to its widespread use with NVMe SSDs. All new functionality is optional. This ECN affects the PCIe 4.0 Base Specification. show less
4.x ECN
Enhanced PCIe Precision Time Measurement (ePTM) ECN
This ECN effects the PCI Express Base Specification,...view more This ECN effects the PCI Express Base Specification, Version 4.0. ePTM is an improvement on the existing Precision Time Measurement capability that provides improved detection and handling of error cases. ePTM quickly identifies and resolves errors that may cause clocks to become desynchronized. show less
4.x ECN
ACS Enhanced Capabilities ECN
This ECN defines four new services under ACS for Dow...view more This ECN defines four new services under ACS for Downstream Ports, primarily to address issues when ACS redirect mechanisms are used to ensure that DMA Requests from Functions under the direct control of VMs are always routed correctly to the Translation Agent in the host. Three of the services provide redirect or blocking of Upstream Memory Requests that target areas not covered by other ACS services. The fourth service enables the blocking of Upstream I/O Requests, addressing a concern with VM-controlled Functions maliciously sending I/O Requests. show less
4.x ECN
PCI Express Architecture Configuration Space Test Specification Revision 4.0, Version 1.0
This document primarily covers PCI Express testing o...view more This document primarily covers PCI Express testing of all defined PCI Express device types and RCRBs for the standard Configuration Space mechanisms, registers, and features in Chapter 6 of the PCI Local Bus Specification (Base 3.x or earlier only) and Chapters 7, 9 (Base 4.x or later only), 10 (Base 4.x or later only) of the PCI Express Base Specification (some additional tested registers are described in other specifications that are referenced in the individual test description). This specification does not describe the full set of PCI Express tests for these devices. show less
4.x Specification
PCI Express Architecture Link Layer and Transaction Layer Test Specification Revision 4.0, Version 1.0
This test specification primarily covers testing of ...view more This test specification primarily covers testing of PCI Express® Device and Port types for compliance with the link layer and transaction layer requirements of the PCI Express Base Specification. Device and Port types that do not have a link (e.g., Root Complex Integrated Endpoints, Root 10 Complex Event Collectors) are not tested under this test specification. While the test environment can accommodate the presence of a Retimer, it will not test the Retimer itself. At this point, this test specification does not describe the full set of PCI Express tests for all link layer or transaction layer requirements. show less
4.x Specification
PCI Express Architecture PHY Test Specification Revision 4.0, Version 1.0
This document provides test descriptions for PCI Exp...view more This document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices. show less
4.x Specification
Manufacturer Test Mode Pin ECN
High Volume Manufacturing (HVM) and other manufactur...view more High Volume Manufacturing (HVM) and other manufacturer test processes benefit from the ability to set Add-in Card (AIC) modes that enable multiplexing of standard connector pins for test specific use. This ECR defines a method to allow the system to enable a Manufacturer Test Mode (MFG) on the AIC through the standard interface connector prior to shipping the AIC. This ECR to the CEM specification is consistent with Manufacturing Mode ECN to the SFF-8639 specification. show less
4.x ECN
PCI Express Card Electromechanical Specification Revision 4.0, Version 1.0 (Clean)
This specification is a companion for the PCI Expres...view more This specification is a companion for the PCI Express® Base Specification, Revision 4.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications. show less
4.x Specification
PCI Express Card Electromechanical Specification Revision 4.0, Version 1.0 (Change Bar)
This specification is a companion for the PCI Expres...view more This specification is a companion for the PCI Express® Base Specification, Revision 4.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications. show less
4.x Specification
Errata for the PCI Express Base Specification Revision 4.0
Final Release against Base Revision 4.0 ...view more Final Release against Base Revision 4.0 show less
4.x Errata
PCI Express Architecture PHY Test Specification Revision 4.0, Version 1.01 (Change Bar)
This document provides test descriptions for PCI Exp...view more This document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices. show less
4.x Specification
PCI Express Architecture PHY Test Specification Revision 4.0, Version 1.01 (Clean)
This document provides test descriptions for PCI Exp...view more This document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices. show less
4.x Specification
Cin Maximum Increase ECN
Smaller lithography has led to smaller pad sizes whi...view more Smaller lithography has led to smaller pad sizes which has increased parasitics on inputs. For the Card Electromechanical Specification, this ECR increases Cin, the maximum input pin capacitance on 3.3 V logic signals (applies to PERST# and PWRBRK#) from 7 pF to 20 pF (see CEM Table 3). For the M.2 specification, this ECR increases M.2 CIN, the maximum input pin capacitance for both 3.3 V logic signal (applies to PERST#, see M.2 Table 4-1) and 1.8 V logic signals (applies to PERST# and PEWAKE# (when used for OBFF signaling), see M.2 Table 4-2) from 10 pF to 20 pF. This capacitance increase is large enough for known upcoming lithographies. It had not been clear what the measurement point was for CIN in CEM or M.2 specifications. This 18 ECN extends the COUT measurement point specified in M.2 to apply to CIN and COUT for both 19 CEM and M.2 specifications. show less
4.x ECN
PCI Express External Cabling Specification Revision 3.0a (Change Bar)
This is a companion specification to the PCI Express...view more This is a companion specification to the PCI Express Base Specification. The primary focus of this specification is the implementation of cabled PCI Express®. No assumptions are made regarding the implementation of PCI Express-compliant Subsystems on either side of the cabled Link (PCI Express Card Electromechanical (CEM), ExpressCard™, ExpressModule™, PXI Express™, or any other form factor). Such form factors are covered in separate specifications show less
4.x Specification
PCI Express Architecture PHY Test Specification Revision 4.0, Version 1.01A (Clean)
This document provides test descriptions for PCI Exp...view more This document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices show less
4.x Specification
PCI Express Architecture PHY Test Specification Revision 4.0, Version 1.01A (Change Bar)
This document provides test descriptions for PCI Exp...view more This document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices show less
4.x Specification
PCI Express M.2 Specification Revision 4.0, Version 1.0 (Change Bar)
The M.2 form factor is intended for Mobile Adapters....view more The M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution. show less
4.x Specification
PCI Express M.2 Specification Revision 4.0, Version 1.0 (Clean)
The M.2 form factor is intended for Mobile Adapters....view more The M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution. show less
4.x Specification
(M.2) | Voltage Indication for PCIe BGA 1113 SSD and 1.0 V PWR3 Support ECN
Proposes repurposing five RFU pins in the Type 1113 ...view more Proposes repurposing five RFU pins in the Type 1113 (11.5mm x 13mm) BGA ball map to be optionally used for indicating PWR1, PWR2, and PWR3 supply voltage requirements to the platform. If this ECR is implemented then all 5 pins need to be implemented. Adds a 1.0 V power supply option for PWR3 for both BGA1113 and BGA1620. show less
4.x ECN
PCI Express SFF-8639 Module Specification Revision 4.0, Version 1.0 (Clean)
The focus of this specification is on PCI Express® (...view more The focus of this specification is on PCI Express® (PCIe®) solutions utilizing the SFF-8639 connector interface. Form factors include, but are not limited to, those described in the SFF-8201 Form Factor Drive Dimensions Specification. Other form factors, such as PCI Express Card Electromechanical are documented in other independent specifications. show less
4.x Specification
M.2 3052 3060 WWAN Module
Add 3052 and 3060 form factors for WWAN modules usin...view more Add 3052 and 3060 form factors for WWAN modules using Socket 2 with Key B and Key C. show less
4.x ECN
PWRDIS Asserted Hold Time Reduction
This ECR establishes two operational modes for use o...view more This ECR establishes two operational modes for use of the Power Disable (PWRDIS) signal. The existing mode allowed use of the signal for coordinated shutdown of the PCIe device, but was optimized for a power-on reset of a non-responsive device. The new mode reduces PWRDIS minimum asserted hold time from 5 s to 100 ms for use in a coordinated shutdown with an emphasis on entry and exit times from D3cold. show less
4.x ECN
PCI Express Architecture PHY Test Specification Revision 4.0, Version 1.2
This document provides test descriptions for PCI Exp...view more This document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0.   show less
4.x Specification
Add core voltage 0.75 V in PWR_3 rail for BGA SSD
Summary of the Functional Changes...view more Summary of the Functional Changes I. Add core voltages 0.75 V in PWR_3 rail for BGA SSD. II. Add new pin configuration including 0.75 V pin. show less
4.x ECN
PCI Express Retimer Test Specification Revision 4.0, Version 1.0
This test specification is intended to confirm if a ...view more This test specification is intended to confirm if a stand-alone Retimer is compliant to the PCI Base Specification. show less
4.x Specification
ATS Memory Attributes ECN, Revision A 4.x ECN
ATS Memory Attributes ECN, Revision A 4.x ECN
Shadow Functions ECN 4.x ECN
PTM Byte Adaptation ECN 4.x ECN
Errata for the PCI Express Base Specification Revision 4.0 4.x Errata
ACS Enhanced Capabilities ECN 4.x ECN
Enhanced PCIe Precision Time Measurement (ePTM) ECN 4.x ECN
Async Hot-Plug Updates ECN 4.x ECN
Errata for the PCI Express® Base Specification Revision 4.0 4.x Errata
Root Complex Event Collector Bus Number Association ECN 4.x ECN
Address Translation Relaxed Ordering ECN 4.x ECN
PCIe Link Activation ECN 4.x ECN
Root Complex Event Collector Bus Number Association ECN 4.x ECN
Address Translation Relaxed Ordering ECN 4.x ECN
https://members.pcisig.com/wg/PCI-SIG/document/11120 4.x ECN
Expansion ROM Validation ECN 4.x ECN
Add core voltage 0.75 V in PWR_3 rail for BGA SSD ECN (rename) 4.x ECN
PWRDIS Asserted Hold Time Reduction (rename) 4.x ECN
1.8V IO for LGAs
This ECN adds 1.8V IO support to Type 1216, Type 222...view more This ECN adds 1.8V IO support to Type 1216, Type 2226, and Type 3026 LGAs. This support adds two previously defined pins to these LGAs: • VIO_CFG, a 1.8V IO support indication (one pin) • VIO 1.8V, a 1.8V IO Voltage source (one pin) The VIO 1.8 V signal is intended as an IO supply and reference voltage for host interface sideband signals PERST#, CLKREQ#, and PEWAKE# and additional signals such as SUSCLK, W_DISABLE1#, W_DISABLE2#. This provides IO voltage flexibility to enable IO voltage levels other than 3.3V in the applicable M.2 form factors. The VIO_CFG signal is intended to provide the Platform an indication of the IO voltage capabilities of the M.2 Adapter installed. In cases where the Platform detects that an incompatible Adapter is installed, the Platform may choose to not power the Adapter or isolate the affected sideband signals to avoid damage or interface instability. show less
4.x ECN
PCI Express M.2 Specification Revision 4.0, Version 1.1
The M.2 form factor is intended for Mobile Adapters....view more The M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution. show less
4.x Specification
PCI Express M.2 Specification Revision 4.0, Version 1.1 (Change Bar Version)
The M.2 form factor is intended for Mobile Adapters....view more The M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution. show less
4.x Specification
Auxiliary Signal Leakage and Capacitance Increase ECN
This ECR increases the specified leakage and capacit...view more This ECR increases the specified leakage and capacitance tolerances for Auxiliary I/O signals. show less
4.x ECN
PCI Express M.2 Specification, Revision 4.0, Version 1.1 Errata 4.x Errata
Increased +3.3 Vaux Current
For the SFF-8639 module (U.2) specification, this EC...view more For the SFF-8639 module (U.2) specification, this ECR increases +3.3 VAux current. The category of SMBus inactive current is eliminated and replaced with a default current of 8 mA. Additionally, the 5 mA active current requirement is eliminated and replaced with a 25 mA requirement if MCTP or I3C Basic traffic is initiated by the platform when Vaux power is enabled while 12V is disabled. show less
4.x ECN
M.2-1A Mid-mount Connector Amperage Improvement
This proposal introduces a new version of the M.2 co...view more This proposal introduces a new version of the M.2 connector with improved amperage per pin to 1 A, card outline changes with increased component area options. show less
4.x ECN
PCI Express M.2 Specification Revision 4.2
The M.2 form factor is intended for Mobile Adapters....view more The M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution. show less
4.x Specification
PCI Express M.2 Specification, Revision 4.2 Errata 4.x Errata
PCI Express Base Specification Revision 5.0, Version 1.0
This specification describes the PCI Express archite...view more This specification describes the PCI Express architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. show less
5.x Specification
PCI Express Base Specification Revision 5.0, Version 1.0 (Change Bar Versions)
There are four informative ...view more There are four informative "changebar" versions of the PCI Express Base 5.0 Specification comparing Base 5.0/1.0 to Base 5.0/0.9 and comparing Base 4.0 and Base 5.0. HTML and PDF versions are provided. Both versions are derived from common source material but have different characteristics, and readers may wish to reference both. These documents are non-normative - the NCB PCI Express Base Specification Revision 5.0, Version 1.0 (NCB-PCI_Express_Base_5.0r1.0-2019-05-22.pdf) is the normative version of this specification. show less
5.x Specification
Errata for the PCI Express Base Specification Revision 5.0 5.x Errata
ATS Memory Attributes ECN, Revision A
Revision A (January 30, 2020) corrects an error in t...view more Revision A (January 30, 2020) corrects an error in the original revision (September 29, 2019). The ATS Memory Attributes Supported field in the ATS Capabilities Register is now assigned bit location 8. It was previously assigned bit location 7. The affected text is highlighted in Table 10-9: ATS Capability Register. show less
5.x ECN
PTM Byte Adaptation ECN
Due to ambiguity in earlier versions of the PCIe Bas...view more Due to ambiguity in earlier versions of the PCIe Base Specification two different interpretations of the byte positions in the PTM ResponseD Message Propagation Delay field have been implemented. This ECR defines mechanisms that new hardware can implement to support the adaptation to either of the interpretations. show less
5.x ECN
Shadow Functions ECN
Shadow Functions are permitted to be assigned only w...view more Shadow Functions are permitted to be assigned only where currently unused Functions reside. The Function declaring the shadowing is permitted to overflow its Transaction ID space over into the Shadow Function. The impetus for defining Shadow Functions is to provide more Transaction ID space without increasing the Tag field, since there are no straightforward means to do that at the current time. show less
5.x ECN
Data Object Exchange (DOE) ECN
This ECR defines an optional Extended Capability str...view more This ECR defines an optional Extended Capability structure and associated control mechanisms to provide System Firmware/Software the ability to perform data object exchanges with a Function or RCRB. To support Component Measurement and Authentication (CMA) accessible in-band via host firmware/software, Data Object Exchange (DOE) is required, and CMA motivates the need for DOE, although broader uses are anticipated. show less
5.x ECN
Component Measurement and Authentication (CMA) ECN
This ECR defines an adaptation of the data objects a...view more This ECR defines an adaptation of the data objects and underlying protocol defined in the DMTF SPDM specification (https://www.dmtf.org/dsp/DSP0274) for PCIe components, providing a mechanism to verify the component configuration and firmware/executables (Measurement) and hardware identities (Authentication). “Firmware” in this context includes configuration settings in addition to executable code. This protocol can be operated via the Data Object Exchange (DOE) mechanism, or through other means, for example via MCTP messaging conveyed using PCIe Messages, or via SMBus, I2C, or other management I/O. Data Object Exchange (DOE) is defined in the Data Object Exchange ECN to the PCIe Base Specification Rev 4.0, 5.0, approved on 12 Mar 2020. show less
5.x ECN
Deferrable Memory Write (DMWr) and Device 3 Extended Capability ECN
This ECN defines a new Request, the Deferrable Memor...view more This ECN defines a new Request, the Deferrable Memory Write (DMWr), that requires the Completer to return an acknowledgement to the Requester, and provides a mechanism for the recipient to defer (temporarily refuse to service) the Request. To provide space for the required control registers, this ECN also defines an Extended Capability, the Device 3 Extended Capability, to provide Device Capabilities 3, Device Control 3, and Device Status 3 registers. This Extended Capability is required for DMWr support, but can also be applied to other uses besides DMWr, and therefore can be implemented by Functions that do not support DMWr. show less
5.x ECN
(PWG) | Translated Memory Requests with PASID ECN
Loosens restrictions on use of PASID to allow PASID ...view more Loosens restrictions on use of PASID to allow PASID to be applied to Memory Requests using Translated addresses (AT=Translated). show less
5.x ECN
(PWG) | Integrity and Data Encryption (IDE) ECN
Integrity & Data Encryption (IDE) provides confi...view more Integrity & Data Encryption (IDE) provides confidentiality, integrity, and replay protection for TLPs. It flexibly supports a variety of use models, while providing broad interoperability. The cryptographic mechanisms are aligned to current industry best practices and can be extended as security requirements evolve. The security model considers threats from physical attacks on Links, including cases where an adversary uses lab equipment, purpose-built interposers, malicious Extension Devices, etc. to examine data intended to be confidential, modify TLP contents, & reorder and/or delete TLPs. TLP traffic can be secured as it transits Switches, extending the security model to address threats from reprogramming Switch routing mechanisms or using “malicious” Switches. Compared to the Member Review copy, and consistent with the “NOTICE TO REVIEWERS” in that copy, this final revision contains significant revisions to the key management protocol in order to align it closely with the DMTF’s Secured Messages using SPDM Specification, which was not available at the time the Member Review copy was prepared. Additionally, the final copy includes significant improvements in protection against Adversary-in-the-Middle attacks, and, consistent with member feedback received in response to the query regarding key size for AES-GCM applied to IDE TLPs, supports only the 256b key size. show less
5.x ECN
Errata for the PCI Express® Base Specification Revision 5.0 5.x Errata
PCI Express Card Electromechanical Specification Revision 5.0
This Card Electromechanical (CEM) specification is a...view more This Card Electromechanical (CEM) specification is a companion for the PCI Express® Base Specification, Revision 5.0. Its primary focus is the implementation of an evolutionary strategy with earlier PCI™ desktop/server mechanical and electrical specifications. show less
5.x Specification
PCI Express Card Electromechanical Specification Revision 5.0 (Change Bar)
This Card Electromechanical (CEM) specification is a...view more This Card Electromechanical (CEM) specification is a companion for the PCI Express® Base Specification, Revision 5.0. Its primary focus is the implementation of an evolutionary strategy with earlier PCI™ desktop/server mechanical and electrical specifications. show less
5.x Specification
(PWG) | Combined Power ECN (Change Bar)
This is a change to the PCI Express Base Specificati...view more This is a change to the PCI Express Base Specification, Revision 5.0. show less
5.x ECN
(PWG) | Combined Power ECN
This is a change to the PCI Express Base Specificati...view more This is a change to the PCI Express Base Specification, Revision 5.0. show less
5.x ECN
Tx Jitter Measurement Methodology at 32.0 GT/s ECN
Describes a method to measure Tx jitter parameters a...view more Describes a method to measure Tx jitter parameters at 32 GT/s accurately by using a Jitter Measurement Pattern. This replaces the S-parameter de-embedding method. In this method, a CTLE-based equalization instead of S-parameter based de-embedding gain filter is applied to the captured Tx waveform to mitigate signal degradation due to frequency-dependent channel loss. The CTLE-based equalization is defined by the 32 GT/s reference CTLE curves. The proposed method with the use of clock pattern in the lane under test and compliance pattern in other lanes avoids the inaccuracy of the S-parameter based de-embedding that results from the amplification of the real-time oscilloscope floor noise by the de-embedding gain filter. The Tx jitter measurement methods for 8.0 and 16.0 GT/s have been kept unchanged. show less
5.x ECN
Fitting-based Tx Preset Measurement Methodology for 8.0, 16.0, and 32.0 GT/s ECN
Introduces a fitting-based Tx preset measurement met...view more Introduces a fitting-based Tx preset measurement methodology that extracts Tx equalization coefficients from measured step responses with and without Tx equalization. Consequently, it overcomes a few limitations of the current DC voltage-level based methodology where the ratio of DC voltage levels of various presets is used to avoid measurement complexity due to high frequency-dependent loss. Since the use of the ratio of DC voltage levels do not guarantee the correct use of Tx equalization coefficients and constant voltage swing across presets, the existing DC voltage-level based measurement methodology may give incorrect results if the Tx equalization coefficients and voltage swing significantly deviate from the intended values for the specified Tx presets. show less
5.x ECN
(CEM WG) | Errata to the PCI Express CEM Specification, Revision 5.0, Version 1.0 5.x Errata
(CEM WG) | Power Excursion Limits for 300-600 W PCIe AICs ECN
This change allows for cards to exceed maximum power...view more This change allows for cards to exceed maximum power levels currently defined in the CEM spec to enable higher performance for certain workloads. This change clearly defines limits for these excursions to allow system designers to properly design power subsystems to enable these excursions. show less
5.x ECN
(PWG) | Relaxed Detect Timing ECN
The long-standing requirement for a component’s LTSS...view more The long-standing requirement for a component’s LTSSM to enter Detect state within 20 ms of the end of Fundamental Reset is relaxed (extended) to 100 ms for components that support >5 GT/s Link speeds. show less
5.x ECN
Integrity and Data Encryption (IDE) ECN – Revision A
Original IDE ECN plus IDE items included in final Ba...view more Original IDE ECN plus IDE items included in final Base 5.0 Errata. Changebar version relative to original IDE ECN also available. show less
5.x ECN
Errata for the PCI Express Base Specification Revision 5.0
...view more Corresponds to Errata included in Base 6.0, Version 0.9 and Version 1.0 show less
5.x Errata
Integrity and Data Encryption (IDE) ECN – Revision A (Change Bar)
This is a change bar version of the Integrity and Da...view more This is a change bar version of the Integrity and Data Encryption (IDE) ECN – Revision A. show less
5.x ECN
Transmitter Jitter requirements at 32.0 GT/s ECN
Transmitter jitter requirements at 32 GT/s are being...view more Transmitter jitter requirements at 32 GT/s are being added for system board and Add-in Card. Affected Document: PCI Express Card Electromechanical Specification Revision 5.0, Version 1.0 show less
5.x ECN
PCI Express Architecture PHY Test Specification, Revision 5.0, Version 1.0
This document provides test descriptions for PCI Exp...view more This document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 5.0. show less
5.x Specification
PCI Express Architecture Configuration Space Test Specification Revision 5.0, Version 1.0
This document primarily covers PCI Express testing o...view more This document primarily covers PCI Express testing of all defined Device Types and RCRBs for the standard Configuration Space mechanisms, registers, and features. show less
5.x Specification
PCI Express Architecture Link Layer and Transaction Layer Test Specification Revision 5.0, Version 1.0
This test specification primarily covers testing of ...view more This test specification primarily covers testing of PCI Express® Device and Port types for compliance with the link layer and transaction layer requirements of the PCI Express Base Specification. show less
5.x Specification
12VHPWR Sideband Allocation and Requirements
Summary of the Functional Changes...view more Summary of the Functional Changes Changing the RFU pin in the 12VHPWR connector sideband to Sense1. Adding 150W and 300W power capabilities to the encoding options for Sense0 and Sense1. Makes Card_CBL_PRES required to be tied to ground with 4.7 kΩ resistor. show less
5.x ECN
TEE Device Interface Security Protocol (TDISP)
This document defines the TEE Device Interface Secur...view more This document defines the TEE Device Interface Security Protocol (TDISP) - An architecture for trusted I/O virtualization providing the following functions: 1. Establishing a trust relationship between a TVM and a device. 2. Securing the interconnect between the host and device. 3. Attach and detach a TDI to a TVM in a trusted manner. show less
5.x ECN
Shadow Functions ECN 5.x ECN
PTM Byte Adaptation ECN 5.x ECN
Expanding Power Excursion Spec to All Power Levels of PCIe AICs and to CEM Connector Power Rails ECN
Expands power excursion to 12V power rail in PCIE CE...view more Expands power excursion to 12V power rail in PCIE CEM connector in addition to 12VHPWR and 48VHPWR connectors but excludes legacy 2x3 and 2x4 auxiliary power connectors from power excursion specification. show less
5.x ECN
12VHPWR Cable Plug Update ECN
This ECN replaces existing drawings for the 12VHPWR ...view more This ECN replaces existing drawings for the 12VHPWR cable plug with 2 different options. show less
5.x ECN
Update to Transmitter Jitter requirements at 32.0 GT/s ECN
This ECR removes the transmitter jitter test require...view more This ECR removes the transmitter jitter test requirement for 32 GT/s systems. Transmitter jitter test remains a requirement for 32 GT/s Add-in Cards. show less
5.x ECN
PCI Express M.2® Specification Revision 5.0, Version 1.0
The M.2 form factor is intended for Mobile Adapters....view more The M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution. show less
5.x Specification
Change Link and Transaction test case 54-20 to informative
Informational testing on test case 54-20 will give D...view more Informational testing on test case 54-20 will give DUT vendor information about their implementation of the capability. Not passing judgement on test case 54-20 will prevent DUTs from incorrect failing the DUT or false passing the DUT at Compliance Workshops. show less
5.x ECN
PCI Express Card Electromechanical Specification Revision 5.1, Version 1.0 CB
This Card Electromechanical (CEM) specification is a...view more This Card Electromechanical (CEM) specification is a companion for the PCI Express® Base Specification, Revision 5.0. Its primary focus is the implementation of an evolutionary strategy with earlier PCI™ desktop/server mechanical and electrical specifications. show less
5.x Specification
PCI Express Card Electromechanical Specification Revision 5.1, Version 1.0 NCB
This Card Electromechanical (CEM) specification is a...view more This Card Electromechanical (CEM) specification is a companion for the PCI Express® Base Specification, Revision 5.0. Its primary focus is the implementation of an evolutionary strategy with earlier PCI™ desktop/server mechanical and electrical specifications. show less
5.x Specification
PCI Express CEM Specification, Revision 5.1 Errata
PCI Express CEM Specification, Revision 5.1 Errata...view more PCI Express CEM Specification, Revision 5.1 Errata show less
5.x Errata
48 V Aux Power Header and Cable Assembly Improvements
This ECR introduces updated dimensioning and toleran...view more This ECR introduces updated dimensioning and tolerances for the 48VHPWR header and plug. The 48VHPWR connector has been removed from the specification. The name for the new connector is 48V1x2. Ordering of the sense pins is changed so that Sense0 and Sense1 pins are located farthest from each other. This reordering is incompatible with the pre-existing connector definition. Per workgroup input, there are no known implementations of the 48VHPWR header and plug as of this publication date. References to external specifications are added. show less
5.x ECN
PCI Express Retimer Test Specification Revision 5.0
This test specification is intended to confirm if a ...view more This test specification is intended to confirm if a stand-alone Retimer is compliant to the PCIe Base Specification. This test specification is not intended to test Retimers based only on the Extension Devices ECN to the PCI Express Base Specification, Revision 3.x. This test specification only covers stand-alone Retimers in common clock mode, and is not intended to test Retimers integrated onto a platform or an add-in card. show less
5.x Specification
PCI Express SFF-8639 Module (U.2) Specification Revision 5.0
The focus of this specification is on PCI Express® (...view more The focus of this specification is on PCI Express® (PCIe®) solutions utilizing the SFF-8639 (also known as U.2) connector interface. Form factors include, but are not limited to, those described in the SFF-8201 Form Factor Drive Dimensions Specification. Other form factors, such as PCI Express Card Electromechanical are documented in other independent specifications. show less
5.x Specification
PCI Express Architecture PHY Test Specification Revision 5.1
This document provides test descriptions for PCI Exp...view more This document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 5.0. This specification does not describe the full set of PCI Express tests and assertions for these devices. show less
5.x Specification
PCI Express M.2 Specification Revision 5.1
The M.2 form factor is intended for Mobile Adapters....view more The M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution. One of the goals for M.2 is to be significantly smaller in the XYZ and overall volume than the HalfMini Card for the very thin computing Platforms (e.g., Notebook, Tablet/Slate Platforms) that require a much smaller solution. show less
5.x Specification
PCI Express External Cabling Specification Revision 5.0, Version 1.0
This is a companion specification to the PCI Express...view more This is a companion specification to the PCI Express Base Specification. The primary focus of this specification is the implementation of cabled PCI Express® . No assumptions are made regarding the implementation of PCI Express-compliant Subsystems on either side of the cabled Link (PCI Express Card Electromechanical (CEM), ExpressCard™, ExpressModule™, PXI Express™, or any other form factor). Such form factors are covered in separate specifications. show less
5.x Specification
PCI Express M.2 Specification, Revision 5.1 5.x Errata
PCI Express Base Specification Revision 6.0, Version 1.0 (Change Bar Versions)
There are two informative "changebar" versions of th...view more There are two informative "changebar" versions of the PCI Express Base 6.0 Specification comparing Base 6.0/1.0 to Base 6.0/0.9 and comparing Base 5.0 to Base 6.0. show less
6.x Specification
PCI Express Base Specification Revision 6.0, Version 1.0
This specification describes the PCI Express® archit...view more This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. This document defines the “base” specification for the PCI Express architecture, including the electrical, protocol, platform architecture and programming interface elements required to design and build devices and systems. show less
6.x Specification
Alternate Protocol DLLP Reservation
CXL 3.0 defines an alternate protocol and has asked ...view more CXL 3.0 defines an alternate protocol and has asked for a DLLP assignment. They want to use a DLLP instead of a Flit_Marker to reduce their latency (this issue is unique to their protocol – PCIe does not have this issue).  show less
6.x ECN
PCI Express® Base Specification Revision 6.1
This document defines the “base” specification for t...view more This document defines the “base” specification for the PCI Express architecture, including the electrical, protocol, platform architecture and programming interface elements required to design and build devices and systems. A key goal of the PCI Express architecture is to enable devices from different vendors to inter-operate in an open architecture, spanning multiple market segments including clients, servers, embedded, and communication devices. The architecture provides a flexible framework for product versatility and market differentiation. show less
6.x Specification
PCI Express® Base Specification Revision 6.1 (Change Bar)
This document defines the “base” specification for t...view more This document defines the “base” specification for the PCI Express architecture, including the electrical, protocol, platform architecture and programming interface elements required to design and build devices and systems. A key goal of the PCI Express architecture is to enable devices from different vendors to inter-operate in an open architecture, spanning multiple market segments including clients, servers, embedded, and communication devices. The architecture provides a flexible framework for product versatility and market differentiation.  show less
6.x Specification
12V-2x6 Connector Updates to PCIe Base 6.0
This ECN defines Connector Type encodings for the ne...view more This ECN defines Connector Type encodings for the new 12V-2x6 connector. This connector, defined in CEM 5.1, replaces the 12VHPWR connector. Update 12VHPWR encoding to reflect published CEM 5.0 (the Base Spec and CEM 5.0 were inconsistent). Update default measurement methodology for Maximum and Sustained power to match existing Form Factor specifications, providing consistency between specifications. show less
6.x ECN
Management Message Passthrough via MMIO Mailbox (MMPT)
This ECR defines an optional mechanism for passing m...view more This ECR defines an optional mechanism for passing management messages between system software and a PCI Function using a mailbox interface in the Function’s memory mapped I/O (MMIO) space. It also includes mechanisms to advertise, locate, and extend MMIO I/O register blocks generically, the definition of the mailbox registers and command interface, and the management message passthrough (MMPT) interface. show less
6.x ECN
Component Measurement and Authentication (CMA-SPDM) Revised
CMA-SPDM defines a mapping of the DMTF SPDM (DSP0274...view more CMA-SPDM defines a mapping of the DMTF SPDM (DSP0274) specification for PCIe implementations. Since the initial publication of CMA-SPDM, multiple revisions of DSP0274 have been published. This set of revisions is intended to align with these updates, with DOE 1.1, and with current industry direction. Highlights include: • Alignment of CMA-SPDM with SPDM 1.2 and DOE 1.1 • Removal of outdated/redundant material, especially material that is now better covered in SPDM itself • Improved clarity of SPDM mapping to data objects • Correcting under-specified areas, especially regarding interoperable algorithm choices • Remove requirements placed on leaf certificates show less
6.x ECN
Chapter 12. Architectural Out-of-Band Management ECN
Form factor specifications will become easier to dev...view more Form factor specifications will become easier to develop because many sideband elements can be incorporated by reference. Commonality will increase, simplifying system design and implementation. Other sections of the Base specification will be enabled to cleanly make use of sideband mechanisms, where appropriate. show less
6.x ECN
PCI Express Base Specification Revision 6.2
This document defines the “base” specification for t...view more This document defines the “base” specification for the PCI Express architecture, including the electrical, protocol, platform architecture and programming interface elements required to design and build devices and systems. A key goal of the PCI Express architecture is to enable devices from different vendors to inter-operate in an open architecture, spanning multiple market segments including clients, servers, embedded, and communication devices. The architecture provides a flexible framework for product versatility and market differentiation. show less
6.x Specification
PCI Express Base Specification Revision 6.2 (Change Bar)
This document defines the “base” specification for t...view more This document defines the “base” specification for the PCI Express architecture, including the electrical, protocol, platform architecture and programming interface elements required to design and build devices and systems. A key goal of the PCI Express architecture is to enable devices from different vendors to inter-operate in an open architecture, spanning multiple market segments including clients, servers, embedded, and communication devices. The architecture provides a flexible framework for product versatility and market differentiation.  show less
6.x Specification
CopprLink Internal Cable Specification for PCI Express 5.0 and 6.0 Version 1.0
The primary objectives of this Internal Cable Specif...view more The primary objectives of this Internal Cable Specification for PCI Express 5.0 and 6.0 document are to provide 32 GT/s and 64 GT/s electrical specifications for mated cable assembly and mated cable connector based on SFF-TA-1016 Specification, specifications of sideband functions for sideband pins allocated in the SFF-TA-1016 Specification, and guidelines for 32 GT/s and 64 GT/s electrical spec compliance testing. show less
6.x Specification
Removing Prefetchable Terminology ECN
The concept of “Prefetchable” MMIO was originally ne...view more The concept of “Prefetchable” MMIO was originally needed to control PCI-PCI Bridges, which were allowed/encouraged to prefetch Memory Read data in prefetchable regions. MMIO that has read side-effects, e.g. locations that auto-increment when read, cannot safely be prefetched from, and so needed to be distinguished from regions that could. Additional uses/meanings evolved outside of the PCI-PCI Bridge context, but were not clearly defined in relation to behaviors outside of the PCI/PCIe fabric itself, leading to much industry confusion. Additionally, the PCI-PCI Bridge specification defined the Type1 (bridge) Function Base/Limit mechanism such that MMIO resources above 4GB can only be “Prefetchable,” and since the <4GB space is very limited by modern standards, it has been strongly encouraged for devices to always declare MMIO resource requests as “Prefetchable.” show less
6.x ECN
CopprLink External Cable Specification for PCI Express 5.0 and 6.0 Version 1.0
The primary objectives of this External Cable Specif...view more The primary objectives of this External Cable Specification for PCI Express 5.0 and 6.0 document are to provide • 32.0 GT/s and 64.0 GT/s electrical specifications for mated cable assembly and mated cable connector based on SFF-TA-1032 Specification, • specifications of sideband functions for sideband pins allocated in the SFF-TA-1032 Specification, and • guidelines for 32.0 GT/s and 64.0 GT/s electrical spec compliance testing. show less
6.x Specification
OHC-E Capability Enumeration ECN
This ECR adds a three-bit field called ‘OHC-E Suppor...view more This ECR adds a three-bit field called ‘OHC-E Support’ in Device Capabilities 3 Register to indicate OHC-E support details in a function. show less
6.x ECN
PCI Express Card Electromechanical Specification Revision 6.0
This specification provides additional capabilities ...view more This specification provides additional capabilities for PCI Express® (PCIe) Add-in Cards (AIC) within the existing framework of legacy system board form factors such as AGP and PCI. The PCI Express solution space was historically confined to Advanced Technology eXtended (ATX) or ATX-based form factors but is now integrated into a broader range of applications. The Balanced Technology Extended (BTX) Interface Specification is acknowledged as another form factor. Other connector and form factors that use PCI Express® signaling, are addressed in separate specifications. show less
6.x Specification
Technology: PCI Firmware
Specification Title Spec Rev
Document Type Release Date
_DSM for Vendor-Specific TPH ST ECN
This ECN is based on the TLP Processing Hint (TPH) o...view more This ECN is based on the TLP Processing Hint (TPH) optional capability. The Steering Tag (ST) field handling is platform specific, and this ECN provides a model for how a device driver can determine if the platform root complex supports decode of Steering Tags for specific vendor handling. show less
3.x ECN
PCI Firmware Specification Revision 3.0
This document describes the hardware independent fir...view more This document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer. show less
3.x Specification
Ignore PCI Boot Configuration_DSM Function
This ECN adds a function to the _DSM Definitions for...view more This ECN adds a function to the _DSM Definitions for PCI to provide an indication to an operating system that it can ignore the PCI boot configuration setup by the firmware during system initialization.  show less
3.x ECN
PCI _OSC Clarifications ECN
This ECN attempts to make clarifications such that t...view more This ECN attempts to make clarifications such that the system firmware and multiple operating systems can have the same interpretation of the specification and work interoperably. show less
3.x ECN
PCI Option ROM CLP
This ECN rectifies the differences between the DMTF ...view more This ECN rectifies the differences between the DMTF SM CLP Specification and its supporting documents with the current PCI Firmware 3.0 Specification. Also, it clarifies the supporting documents required for successfully implementing CLP in an X86 PCI FW 3.0 compatible option ROM. show less
3.x ECN
ACPI Additions for ASPM, OBFF, LTR ECNs
A number of PCIe base specifications ECNs have been ...view more A number of PCIe base specifications ECNs have been approved that require software support. In some cases, platform firmware needs to know if the OS running supports certain features, or the OS needs to be able to request control of certain features from platform firmware. In other cases, the OS needs to know information about the platform that cannot be discovered through PCI enumeration, and ACPI must be used to supply the additional information. show less
3.x ECN
PCI Firmware Specification Revision 3.1
This document describes the hardware independent fir...view more This document describes the hardware independent firmware interface for managing PCI™, PCI-X, and PCI Express® systems in a host computer. show less
3.x Specification
PCIe Hot Plug ECN
This ECN affects the PCI Firmware Specification v3.1...view more This ECN affects the PCI Firmware Specification v3.1 and allows certain errors to be suppressed by platform if software stack ensured error containment. Also removes the implementation note in section 4.5.2.4 which is not representative of OS behavior. show less
3.x ECN
PCI Firmware Specification Revision 3.2
This document describes the hardware independent fir...view more This document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.  show less
3.x Specification
_DSM Additions for Runtime Device Power Management
This ECN adds two capabilities by way of adding func...view more This ECN adds two capabilities by way of adding functions to the PCI Firmware Spec defined _DSM definition.  show less
3.x ECN
Enabling Multiple Base Addresses per PCI Segment Group ECN
The changes affect the PCI Firmware Specification, R...view more The changes affect the PCI Firmware Specification, Revision 3.2 and enable the MCFG table format to allow for multiple memory mapped base address entries, instances of Table 4-3, per single PCI Segment Group.  show less
3.x ECN
Downstream Port Containment Related Enhancements ECN
The changes effect the PCI Firmware Specification, R...view more The changes effect the PCI Firmware Specification, Revision 3.2 and will enable the Operating System to advertise its Downstream Port containment related capabilities to the firmware. It also enables the Operating System and the Firmware to negotiate ownership of Downstream Port Containment extended capability register block and collaboratively manage Downstream Port Containment events. show less
3.x ECN
_HPX and PCIe Completion Timeout related _OSC Enhancements ECN
Changes are requested to be made to Section 4.5.1, _...view more Changes are requested to be made to Section 4.5.1, _OSC Interface for PCI Host Bridge Devices and Section 4.5.2.4 Dependencies Between _OSC Control Bits. The changes will enable the Operating System to advertise if it is capable of support _HPX PCI Express Descriptor Setting Record (Type 3) to the firmware. It also enables the Operating System and the Firmware to negotiate ownership of the PCIe Completion Timeout registers.  show less
3.x ECN
Clarifications to _DSM Function 5 ECN
Changes are requested to clarify Section 4.6.5....view more Changes are requested to clarify Section 4.6.5. There is a lot of confusion about where the _DSM object should be located and what the function 5 means. This change Notice proposes no functional changes. show less
3.x ECN
_DSM Additions for PCIe SSD Status LED Management ECN
This ECN adds new capabilities by way of adding new ...view more This ECN adds new capabilities by way of adding new Device Specific Method (_DSM) to the PCI Firmware Spec. show less
3.x ECN
_DSM Function Revision Clarifications ECN
Since the 3.2 release of the Firmware Specification,...view more Since the 3.2 release of the Firmware Specification, several ECRs have been submitted which add _DSM functions or modify existing Functions. The Revision value for each added/modified Function has been included in each ECR, but the value has been applied in a manner inconsistent with previous revisions of the Specification. show less
3.x ECN
System Firmware Intermediary (SFI) _OSC and DPC Updates ECN
Changes are requested to be made to Section 4.5.1, _...view more Changes are requested to be made to Section 4.5.1, _OSC Interface for PCI Host Bridge Devices and Section 4.5.2.4 Dependencies Between _OSC Control Bits. The changes will enable the Operating System and system firmware to negotiate ownership of the System Firmware Intermediary (SFI) Extended Capability Structure. show less
3.x ECN
(Firmware WG) | PCI Firmware Specification Revision 3.3 (Change Bar)
This document describes the hardware independent fir...view more This document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer. show less
3.x Specification
(Firmware WG) | PCI Firmware Specification Revision 3.3 (Clean)
This document describes the hardware independent fir...view more This document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer. show less
3.x Specification
Revised _DSM for Cache Locality TPH Features ECN
This ECN extends the functionality provided by the T...view more This ECN extends the functionality provided by the TPH Features _DSM introduced in Revision 3.3 of the PCI Firmware Specification. show less
3.x ECN
Spec Language Update ECR
Update the PCI Firmware Specification to remove offe...view more Update the PCI Firmware Specification to remove offensive terms and adopt inclusive language. This follows a similar update that was implemented in the PCI Base specification. show less
3.x ECN
DSM to Query Platform RP PIO Error Reporting Capabilities ECN
This ECN defines a _DSM interface for the OS to lear...view more This ECN defines a _DSM interface for the OS to learn whether the platform supports generation of synchronous processor exceptions. If firmware has granted the OS control of the DPC Capability (see _OSC Control[7]) and the platform supports generation of synchronous processor exceptions for an RP PIO error type, the OS may set the corresponding RP PIO Exception bit. If the OS does not have control of the DPC Capability, it may read the RP PIO Exception Register to learn how the platform will report RP PIO errors. show less
3.x ECN