PCI-SIG Developers Conference 2015 Agenda

The sessions below are categorized by track subject according to the following key:

(1) PCI Express
(2) PCI-SIG Architecture
(3) Members Implementation
(4) Members Implementation

Day One - Tuesday, June 23, 2015
Time Title
8:00 am - 9:00 am
9:00 am - 9:30 am		 Registration in Foyer
Introductory Keynote / Annual Members Meeting
9:30 am - 10:30 am (1) PCIe 4.0 Electrical Update    
(2) PCI-SIG Architecture Overview   
(3) Extending Reach of PCI Express Links Using Linear Equalization

10:30 am - 11:30 am

(1) PCIe CEM 4.0 Previews    
(2) PCI Express Basics    
(3) Enabling Complex PCI Express 4.0 Design Validation    
(4) PCIe Protocol Usage for the NVMe User
11:30 am - 1:00 pm Lunch and Exhibit
1:00 pm - 2:00 pm (1) PCIe 3.0 Compliance     
(2) PCIe Electrical Basics    
(3) Accurate Modelling of PCIe 3.0 Analog Buffers
(4) PCI Express 16GT/s Design for Reliability
2:00 pm - 3:00 pm (1) PCIe 4.0 PHY Logical   
(2) New PCI-SIG Website    
(3) Comparing Methods for PCIe 4.0 Rx Test Calibration at 16GT/s    
(4) Testing PCIe Endpoints in Agnostic Environments     
3:00 pm - 3:30 pm PM Break and Exhibit
3:30 pm - 4:30 pm (1) PCIe 4.0 Protocol Update    
(2) PCIe Cable Update    
(3) Designing a Custom PCIe Switch    
(4) Long Tail Equalization for Future PCIe Data Rates
4:30 pm - 5:30 pm PCIe 4.0 Panel Discussion
5:30 pm - 7:00 pm Evening Mixer
Day Two - Wednesday, June 24, 2015
Time Title

 9:00 am - 10:00 am

(1) PCIe 4.0 Electrical Update    
(2) PCI-SIG Architecture Overview    
(3) Distributed PCI Express Switch over 40G Ethernet with Bus Encryption    
(4) Tuning Power Consumption of PCIe Devices
10:00 am - 10:30 am AM Break and Exhibit
10:30 am - 11:30 am (1) PCIe CEM 4.0 Previews    
(2) PCIe Electrical Basics    
(3) Using PCIe in Mobile Devices    
(4) Emulating a PCIe 4.0 Controller on a Real System
11:30 am - 12:30 pm (1) PCIe 3.0 Compliance     
(2) PCI Express Basics    
(3) Increasing System Performance Using PCIe as an Interconnect Fabric     
(4) Signal Integrity Analysis Flow for PCIe 3.0 Testing    
12:30 pm - 1:30 pm Lunch and Exhibit
1:30 pm - 2:30 pm (1) PCIe 4.0 PHY Logical   
(2) New PCI-SIG Website    
(3) PCIe over Fiber: Challenges and Implementation    
(4) Replay and Debug of Post Silicon Bugs in Simulation
2:30 pm - 3:30 pm (1) PCIe 4.0 Protocol Update    
(2) PCIe Cable Update    
(3) Bridging the Simulation and Measurement Gap    
(4) Leveraging Advanced Triggering in PCI Express Protocol Analyzers    
3:30 pm - 4:00 pm PM Break
4:00 pm - 5:00 pm
 		 (3) Using Bifurcation for Data Acquisition at the Large Hadron Collider    
(4) Implementing PCIe 3.1 Protocol ECN Functions