By Al Yanes, PCI-SIG Board Chair and President

I’m pleased to share that PCI-SIG^® continues to make great progress on the development of our next generation of PCIe^® technology – the PCIe 6.0 specification. First announced three months ago during our U.S. Developers Conference in June, our members have fast-tracked development and Revision 0.3 of the specification is now complete and available to PCI-SIG member companies for review and input. This milestone of delivering the 0.3 spec in Oct 2019 validates our projection that we will be able to complete the final specification by 2021.

PCIe 6.0 technology will double the data rate to 64 GT/s while maintaining backward compatibility with all previous spec generations. Two of the key changes that we’re implementing include PAM-4 (Pulse Amplitude Modulation with 4 levels) encoding and low-latency Forward Error Correction (FEC) with additional mechanisms to improve bandwidth efficiency.

PCI-SIG has an extremely robust and proven spec development process that has served us well over the years and led to PCIe becoming the de facto interconnect technology in the industry. Our one-tier membership model also means that every member company has the opportunity to contribute to the spec development process. You can view the complete list of our 800+ member companies here. If your company is on the list, I invite you to get involved. Companies that are interested in becoming members can find information on how to join on our website here.

I’d like to thank all of our members who have invested their knowledge and time in developing the PCIe 6.0 spec. For more information on PCIe technology, visit www.PCI-SIG.com.