By Al Yanes, PCI-SIG® President and Chairman 

Our PCI-SIG® members have been hard at work. In 2017, we delivered PCI Express® 4.0 with its 16 GT/s, while also diving headfirst into PCI Express 5.0 development – first announced at our annual PCI-SIG DevCon in June 2017. With data-hungry applications like artificial intelligence, machine learning, enterprise servers and more, growing in popularity and capabilities, we knew that it was only a matter of time before the market would demand greater bandwidth.

Thanks to the diligence and dedication of our workgroups, I’m pleased to announce that the feature complete PCIe® 5.0, Version 0.9 has now been published to members. This is a great indicator that PCI-SIG will be able to meet its goal of doubling bandwidth—from 16 GT/S to 32 GT/s—in a record less than two years.

PCIe 5.0 delivers a speed upgrade that will reach a data rate of 32 GT/s and offer adaptable lane configurations, while maintaining our low power goal. The new spec builds off of PCIe 4.0, which already supports higher speeds via extended tags and credits. The PCIe 5.0 specification touts a variety of great features: 

• Electrical changes to improve signal integrity and mechanical performance of connectors
• CEM connector targeted to be backwards compatible for add-in cards
• Maintains backward compatibility with PCIe 4.0, 3.x, 2.x and 1.x

We are excited about the revolutionary and unprecedented capabilities of PCIe 5.0 and are on target to publish PCIe 5.0, Version 1.0 in the first quarter of 2019.

Visit our website at https://pcisig.com/ to learn more about how you can become a member and be one of the first to access the final PCIe 5.0 specification.