Author’s Note: This blog discusses new functionality introduced in the PCIe 6.0 specification, but please note that the PCIe 6.0.1 and PCIe 6.1 specification revisions have been published. Developers should always work from the latest revision to ensure they see all specification errata.

The PCI Express^® (PCIe^®) 6.0 specification, in addition to doubling the raw bandwidth compared to PCIe 5.0 architecture, includes many functional enhancements. This blog introduces key new functionality, impacting both software and hardware.

Maintaining backwards compatibility remains a strong value proposition for PCI-SIG^®, and PCIe technology has maintained software backwards compatibility, beginning with the initial release of PCI in the early 1990’s through today. It is challenging to maintain backwards compatibility while serving evolving industry needs and having a means to differentiate “new” and “old” implementations is key. 

Introducing Flit Mode

In the Physical Logical Layer (PHY), PCIe 6.0 specification introduces “Flit Mode” as a new data stream mode. The concept of Flit Mode support goes beyond the Physical Layer, however, and as applied in the PCIe 6.0 specification, indicates “this is new hardware.” This is used as a condition to place requirements for consistency on new hardware while allowing existing implementations to remain compliant. For a hardware block, Flit Mode support does not require there to be a Link associated with a Function. For example, a Root Complex Integrated Endpoint (RCiEP) can indicate Flit Mode support. For Functions associated with a Link, not all new capabilities require the Link to actually operate in Flit Mode, although some do. It is also important to note that, for Functions associated with a Link, it is possible to operate the Link in Flit Mode at any speed.

Support for 14 Bit Tags

For RCiEPs and devices with Links, Flit Mode enables 14-bit tag support. Having more tags enables more outstanding non-posted requests, enabling better performance. Systems with deep-switch topologies and/or multiple retimers are particularly expected to see performance benefit from 14b tags. As with 10b tags, which were introduced in PCIe 4.0 specification, system software will need to enable 14b tags. With Flit Mode, there are improvements in the mechanisms for controlling and optimizing Max_Payload_Size (MPS). These improvements do not impact backwards compatibility, but system software will need to change to take advantage of them. This includes the ability to change MPS values without quiescing, support for systems with different MPS settings for different, and the ability for software to modify MPS settings without quiescing traffic first.

Device Readiness Status Functionality.

Hardware support for Device Readiness Status (DRS) is new required functionality that doesn’t depend on the Link operating in Flit Mode. Timer-based mechanisms for determining when a device or Function is ready have the inherent flaw that in some cases the timeout value is longer than needed, while in other cases it may not be long enough. Sometimes, the time required varies based on conditions that are not easily predicted, which can result in intermittent failures; for example, when a device takes an unusually long time to initialize itself due to some internal condition leading to the system timing-out that device. DRS, which was introduced as an optional feature years ago, provides a positive confirmation of device readiness. With system firmware/software support, DRS enables the system to proceed without unneeded delay with devices that are ready quickly, while ensuring correct functionality for devices that are slower than allowed by the fixed-time limits in previous versions of the specification.

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