PCI Express^® – also known as PCIe – used to get a bad rap for being power hungry on servers and PCs. But I’m happy to say that this is no longer the case. Are you aware that PCIe today is extremely power efficient with built-in low power features? By delivering an I/O technology that delivers high performance, low cost AND low power, PCI-SIG has ensured that PCIe is the interconnect of choice – across multiple devices, including smartphones, tablets, IoT, laptops, and more. On a mobile phone for instance, low power is a stringent requirement, and running PCIe delivers the best of both worlds – a high performance solution with low power options.

Let’s take a closer look at how PCIe supports low power devices and applications.

PCI-SIG continually evolves the PCIe specification to improve performance, increase efficiency, and lower power consumption to satisfy the very divergent needs of many different applications. Since the PCIe 3.0 spec, PCI-SIG has focused on reducing power consumption while the PCIe interface is active to enable better platform power management. I’ll give you a quick overview of some definitions and how they work.

The Latency Tolerance Reporting (LTR) mechanism allows the host to decide how long to wait before servicing the interrupt from the device in order to coordinate multiple devices and achieve the maximum power optimizations for the system.

• L0 – a link which is operating normally
• L1 – a link state where no data is being transferred so key portions of the PCIe transceiver logic can be turned off
• L2 – a link state identical to L3 but in which power has not (yet) been removed
• L3 – when the device is powered off
• L0s – a link state where data may be being transferred in one direction but not the other, so the two devices on a link can each independently idle their transmitter

And then there are the sub-states…

As the industry evolved to more battery-powered devices such as mobile phones and other handheld/mobile devices that need to power on quickly, the focus of power management shifted from gross on-vs-off to finer-grained, moment by moment switching. It became clear to PCI-SIG that for these applications, L2 resume latencies were too high to allow its use for this rapid and frequent state switching, while L1 power savings were too low to meet the device power consumption goals. An innovative solution to this conundrum came in the form of what we call the L1 sub-states.

The fundamental idea behind L1 sub-states is to use something other than the high-speed logic inside the PCIe transceivers to wake the devices. The goal is to achieve near zero power consumption with an active state.

That is done by adding additional functionality to an existing PCIe pin (CLKREQ#) to provide a very simple signaling protocol. This allows the PCIe transceivers to turn off their high-speed circuits and rely on the new signaling to wake them up again. In fact, two of these new sub-states were defined: L1.1 and L1.2 providing their own power vs. exit latency trade-off choices. Both L1.1 and L1.2 permit the PCIe transceivers to turn off their PLLs along with their receivers and transmitters, while L1.2 even allows turning off the common mode keeper circuits.

The results are dramatic. Efficient circuit design and modern silicon processes mean that a representative PCI Express 4.0 x4 PHY (4 transceivers plus related digital logic for four lanes) running at the full 16GT/s data rate in L0 consumes somewhere in the range of 400-500mW. Utilizing L1.1, the same PHY’s power consumption drops by a factor of around 20x to consume only 20-30mW. Accepting the slightly longer exit latency of L1.2 permits power consumption to fall by another 10x to a mere 2-3mW.

The figure below shows the low power solutions available with the existing L1 state compared to using L1 sub-states. It is expected that the power savings scale linearly for multi-lane links and implementing the L1 sub-states feature reduces power consumption at the increase of the L1 exit latency. Implementing L1 sub-states is key to reducing power consumption for mobile designs using PCIe.

Table 1: Comparison of proposed solutions

The low exit latencies and tremendous power savings of the L1 sub-states feature, combined with PCI Express’ load/store architecture and upcoming 32GT/s speed provide the optimal interface for use in mobile devices, storage, compute acceleration, networking and other high-speed devices well into the future.

Learn more about Low Power Features through our new video series on the PCI-SIG YouTube channel. I also encourage you to learn more about PCIe at www.PCISIG.com, and to stay up to date on all the latest PCI-SIG developments by following us on Twitter and LinkedIn.