Frequently Asked Questions

The following FAQ list was generated using standard responses provided to PCI-SIG members by Technical Support and PCI-SIG Administration. For questions relative to the PCI Specifications, please reference the specifications themselves as the authoritative text. 

PCI Express - 6.0

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What are the new features in the PCIe 6.0 specification?

The PCIe 6.0 specification introduces PAM4 (Pulse Amplitude Modulation with 4 levels) signaling, low-latency Forward Error Correction (FEC) and Flit (Flow Control Unit)-based encoding.
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Why does PCIe 6.0 specification utilize PAM4 signaling over NRZ signaling?

PAM4 (Pulse Amplitude Modulation with 4 Levels) is a multilevel signal modulation format used to transmit data. NRZ uses two levels of signaling, while PAM4 uses four levels. It packs two bits of information into the same amount of time on a serial channel.  The utilization of PAM4 allows the PCIe 6.0 specification to reach 64 GT/s data rate and up to 256 GB/s bidirectional bandwidth via a x16 configuration.
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What is Flit Mode and why did PCI-SIG move to this unit of data exchange?

Flit (Flow Control Unit) mode is the unit of data exchange in the PCIe 6.0 specification. PCI-SIG adopted a 256-Byte Flit structure, which includes the variable-sized Transaction  Layer Packets (TLPs) and Data Link Layer Payloads (DLLPs). This is a necessary change due to the move to PAM4 encoding and Forward Error Correction (FEC), which only works on fixed-size data packets. Flit Mode is required for 64 GT/s PAM4 and is supported at all Link speeds. Once a Link trains to Flit Mode, it will stay in Flit Mode as long as that Link remains LinkUp.
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What is Forward Error Correction (FEC) and how is it utilized in the PCIe 6.0 specification?

Lightweight Forward Error Correction (FEC) and strong Cyclic Redundancy Check (CRC) are the two primary methods used in the PCIe 6.0 specification to correct errors. With the 64 GT/s data rate enabled by PAM4 encoding in the PCIe 6.0 specification, the bit error rate (BER) was several orders of magnitude higher than the 10-12 BER in all prior generations. FEC and CRC mitigate the bit error rate and allow the PCIe 6.0 specification to reach new levels of performance. Flit Mode supports the higher BER expected in PAM4 (10-6 vs 10-12 in NRZ). This can provide increased resilience in NRZ environments.