Frequently Asked Questions
The following FAQ list was generated using standard responses provided to PCI-SIG members by Technical Support and PCI-SIG Administration. For questions relative to the PCI Specifications, please reference the specifications themselves as the authoritative text.
PCI Express - 6.0
 What is the PCI Express (PCIe) 6.0 specification? The PCI Express 6.0 specification is the latest generation of PCIe technology, the ubiquitous and general-purpose PCI Express I/O specification. The PCIe 6.0 specification supports data-intensive markets like data centers, artificial intelligence/machine learning, HPC, automotive, IoT, and military aerospace. |
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Why is a new generation of PCIe architecture needed? Heterogeneous computing applications like artificial intelligence, machine learning and deep learning require a high-performance, low-latency I/O interconnect with additional performance over PCIe 5.0. |
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What are the initial target applications for the PCIe 6.0 architecture? The initial target applications of PCIe 6.0 technology include servers, AI/ML, networking and storage in data-intensive markets like data center, HPC, industrial, automotive and Military/Aerospace. |
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What is the bit rate for the PCIe 6.0 specification? How does it compare to previous generations of PCIe technology? The PCIe 6.0 specification supports a data rate of 64 GT/s and up to 256 GB/s via a x16 configuration, while providing low latency, minimal complexity and reduced bandwidth overhead. PCIe 6.0 technology delivers a doubling of the 32 GT/s and 128 GB/s bit rate of the PCIe 5.0 specification. |
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What are the new features in the PCIe 6.0 specification? The PCIe 6.0 specification introduces PAM4 (Pulse Amplitude Modulation with 4 levels) signaling, low-latency Forward Error Correction (FEC) and Flit (Flow Control Unit)-based encoding. |
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Will PCIe 6.0 products be compatible with previous generations? Yes, PCIe 6.0 products will interoperate and maintain backwards compatibility with all previous generations of PCI Express technology. |
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Will there be a new compliance specification developed for the PCIe 6.0 specification? When will compliance testing begin? Yes, for each revision of the base specification, PCI-SIG develops compliance tests and related collateral consistent with the requirements of the new architecture. All of these compliance requirements are incremental in nature and build on the prior generation of the architecture. PCI-SIG anticipates releasing compliance specifications as they mature along with corresponding tests and measurement criteria. PCIe 6.0 Preliminary FYI testing is anticipated to begin in 2023. |
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What are the industry benefits of implementing PCIe 6.0 technology? PCIe 6.0 technology is cost-effective and scalable. By adopting PCIe 6.0 technology in their roadmaps, companies can future-proof their products and offer customers the high bandwidth and low latency technology they need. |
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When do you anticipate products utilizing PCIe 6.0 technology will enter the market? The general timeline is 12-18 months after the release of the final specification. |
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Why does PCIe 6.0 specification utilize PAM4 signaling over NRZ signaling? PAM4 (Pulse Amplitude Modulation with 4 Levels) is a multilevel signal modulation format used to transmit data. NRZ uses two levels of signaling, while PAM4 uses four levels. It packs two bits of information into the same amount of time on a serial channel. The utilization of PAM4 allows the PCIe 6.0 specification to reach 64 GT/s data rate and up to 256 GB/s bidirectional bandwidth via a x16 configuration. |
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What is Flit Mode and why did PCI-SIG move to this unit of data exchange? Flit (Flow Control Unit) mode is the unit of data exchange in the PCIe 6.0 specification. PCI-SIG adopted a 256-Byte Flit structure, which includes the variable-sized Transaction Layer Packets (TLPs) and Data Link Layer Payloads (DLLPs). This is a necessary change due to the move to PAM4 encoding and Forward Error Correction (FEC), which only works on fixed-size data packets. Flit Mode is required for 64 GT/s PAM4 and is supported at all Link speeds. Once a Link trains to Flit Mode, it will stay in Flit Mode as long as that Link remains LinkUp. |
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Can Flit Mode and non-Flit Mode Links intercommunicate? Yes, automatic translation occurs at the boundaries |
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Does Flit Mode support error injection? Yes, Flit Mode supports an optional error injection mechanism. |
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What software changes were needed to take advantage of Flit Mode? A great deal of care has been taken to avoid significant impacts to existing software, but some changes could not be avoided in order to take full advantage of Flit mode. Here are some examples:
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Were bit tags adjusted in the PCIe 6.0 specification? Bit tags were increased to 14 bits to support a larger number of outstanding non-posted requests. We anticipate this wider size to work for at least the next generation as well. |
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What is Forward Error Correction (FEC) and how is it utilized in the PCIe 6.0 specification? Lightweight Forward Error Correction (FEC) and strong Cyclic Redundancy Check (CRC) are the two primary methods used in the PCIe 6.0 specification to correct errors. With the 64 GT/s data rate enabled by PAM4 encoding in the PCIe 6.0 specification, the bit error rate (BER) was several orders of magnitude higher than the 10-12 BER in all prior generations. FEC and CRC mitigate the bit error rate and allow the PCIe 6.0 specification to reach new levels of performance. Flit Mode supports the higher BER expected in PAM4 (10-6 vs 10-12 in NRZ). This can provide increased resilience in NRZ environments. |
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How can I get a copy of the PCIe 6.0 specification? The final specification is available to all PCI-SIG members; join PCI-SIG to receive a copy. Members can download the specification here. |
