A PCIe Link consists of 1, 2, 4, 8, 12, 16, or 32 Lanes, all operating at one of the supported signaling rates.

• PCIe 1.0 provided an effective 2.5 Gigabits/second/Lane/direction of raw bandwidth.
• PCIe 2.0 added support for 5.0 Gigabits/second/Lane/direction of raw bandwidth.
• PCIe 3.0 added support for 8.0 Gigabits/second/Lane/direction of raw bandwidth.
• PCIe 4.0 added support for 16.0 Gigabits/second/Lane/direction of raw bandwidth.
• PCIe 5.0 adds support for 32.0 Gigabits/second/Lane/direction of raw bandwidth.

A PCIe 5.0 Link consisting of 32 Lanes and operating at a bit rate of 32 GT/s provides an effective raw bandwidth of 128 Gigabytes/second in each direction simultaneously. 

PCI-SIG responds to the needs of its members. As applications evolve to consume the I/O bandwidth provided by the current generation of the PCIe architecture, PCI-SIG begins to study the requirements for technology evolution to keep abreast of performance and feature requirements.

PCI-SIG released the PCIe 5.0 specification on May 22, 2019.

As with prior generations, PCIe 5.0 adds some new optional capabilities and features. These include:

• Alternate protocol support – This feature allows non-PCIe protocols to be based on the high-performance and robust PCIe PHY layer. This allows such protocols to be developed much more quickly.
• Bypass Link equalization options – Two equalization bypass options are added: No Equalization Needed, and Equalization Bypass to Highest Data Rate. These bypass options can be used to reduce the time needed to bring up a PCIe Link to its highest data rate at start-of-day.
• Precoding – Added to avoid LCRC/CRC aliasing for cases where a received clock-like bit pattern can lead to contiguous burst errors.
• Component Measurement and Authentication (CMA) – Added to PCIe 5.0 by way of an Engineering Change Notice (ECN), CMA provides the mechanisms to perform security exchanges with a component or a Device Function. This capability, for example, provides the means to establish the hardware and firmware identities of a Function before assigning it to a Virtual Machine.   
• Integrity and Data Encryption (IDE) – Added to PCIe 5.0 by way of an ECN, this capability provides confidentiality and integrity protection for communications between two Ports connected through one or more PCIe Links.

For certain Decision Feedback Equalizer (DFE) settings, certain received bit patterns, such as clock patterns, can cause contiguous burst errors, which in turn can cause LCRC/CRC aliasing. Precoding involves XORing the current bit with the previous bit. That has the effect of converting long contiguous burst errors into two random bit flips that can be reliably detected by CRC. PCIe 5.0 adds the ability for Link partners to request precoding at data rates where one partner or the other requires it.

PCI-SIG is proud of its long heritage of developing compatible architectures and its members have consistently produced compatible and interoperable products. In keeping with this tradition, the PCIe 5.0 architecture is compatible with prior generations of this technology, from software to clocking architecture to mechanical interfaces. PCIe 1.x, 2.x, 3.x, and 4.x cards will seamlessly plug into PCIe 5.0-capable slots and operate at the highest performance levels possible. Similarly, all PCIe 5.0 cards will plug into PCIe 1.x-, PCIe 2.x-, PCIe 3.x- and PCIe 4.x-capable slots and operate at the highest performance levels supported by those configurations.

The PCIe 5.0 specification addresses the many applications pushing for increased bandwidth at a low cost, including server, workstation, desktop PC, notebook PC, tablets, embedded systems, peripheral devices, high-performance computing markets, and more. The target implementations are entirely at the discretion of the designer.

PCI-SIG attempts to define and evolve the PCIe architecture in a manner consistent with low-cost and high-volume manufacturability considerations. While PCI-SIG cannot comment on design choices and implementation costs, optimized silicon, die size, and power consumption continue to be important considerations that inform PCIe specification development and architecture evolution.

For each new PCIe generation, PCI-SIG develops compliance tests and the related collateral consistent with the requirements of the new architecture. All these compliance requirements are incremental in nature and build upon the prior generation of the architecture. PCI-SIG releases compliance specifications as they mature along with corresponding tests and measurement criteria. Each revision of the PCIe technology maintains its own criteria for product interoperability and admission into the PCI-SIG integrators List.

Official Compliance Testing for PCIe 5.0 has been available since April 2022 and many PCIe 5.0 compliant systems, components, and add-in cards have already been added to the Integrators List.

Retimers were introduced with PCIe 4.0. Up to two Retimers are allowed between the Upstream Port and the Downstream Port of a Link. They are used when necessary to reliably extend the achievable channel length between two PCIe Ports. PCIe 4.0 and PCIe 5.0 Retimers are Physical Layer protocol aware. That is, they participate in Link Equalization, and they adjust their data rate of operation and their Link width in concert with the Upstream and Downstream Ports of the Link.