By: Hope Bovenzi, Strategic Marketing, Astera Labs

The PCI Express^® (PCIe^®) 6.0 specification will provide multiple features, including Transaction Layer Packet (TLP) payload, encoding and decoding, shared credit pooling, Forward Error Correction (FEC), CRC error correction, and more.

PCI-SIG^® has shifted to virtual events for the 2020 calendar year and our first major members event was the Virtual PCI-SIG Developers Conference.

The SD Association (SDA) recently announced SD Express, which adds the PCI Express^® and NVMe™ interfaces to the SD interface. The PCIe^® interface delivers transfer rates up to 985 megabytes per second (MB/s) and supports backward compatibility with existing SD hosts.

This is already shaping up to be a busy year for PCI-SIG^® with the pending release of the PCI Express^® 5.0 specification targete