PCIe® 5.0 Protocol and Electrical Compliance Testing Deep Dive Webinar Q&A

  • Posted on: 29 March 2023
  • By: Anthony Mickens and Gordon Getty, Teledyne LeCroy

In 2022, PCI-SIG® introduced PCI Express® (PCIe®) 5.0 Compliance Testing to members. PCIe 5.0 specification official testing includes a maximum link speed of 32 GT/s. The recent PCIe 5.0 Protocol and Electrical Compliance Testing Deep Dive webinar presented by Teledyne LeCroy gave attendees an overview of Protocol and Electrical Compliance Testing for PCIe 5.0 products and systems. This blog provides answers to questions we weren’t able to answer during the live webinar.

Protocol Testing Questions

  1. Why does the PCIe 5.0 test not use an inter-symbol interference (ISI) board?
    • The ISI board is only used for Receiver Bit Error Rate (BER) and Link Equalization Tests. The ISI board isn’t used for the PCIe 5.0 Signal Quality test because the oscilloscope embeds an s-parameter file to the signal being measured. The s-parameter file to be used is determined by the values entered into the fixture characterization spreadsheet which is provided by PCI-SIG.
  2. What does the compliance pattern look like? Where can I find info on the patterns for different generations?
    • The 128b/130b encoded Compliance Pattern is defined in Section 4.2.10 in the PCI Express 5.0 Base Specification Version 1.0. Other patterns are defined before and after Section 4.2.10.
  3. Is the compliance pattern Pseudorandom Binary Sequence (PRBS)11, PRBS31 or anything else?
    • The exact breakdown of the Compliance Pattern can be found in Section 4.2.10 in the PCI Express 5.0 Base Specification Version 1.0.
  4. Can we use SigTest Phoenix to do transmitter (Tx) receiver (Rx) post-processing for M.2 PCIe 5.0 specification?
    • SigTest Phoenix version 5.1.04 currently only supports measurements for Card Electromechanical (CEM) PCIe 5.0 specification.

Electrical Testing Questions

  1. For a x4 lane, which would be considered the middle lane for electrical testing?
    • Devices with a link width of 2 will be tested on both lanes. For a x4 configuration, link width lanes 0 and 3 are tested and for link widths greater than x4, lanes 0, lane N-1 and lane N/2 -1 are tested, where N is the maximum link width. For example, a x16 wide connection is tested at lane 0, lane 15 (16-1) and lane 7 (16/2-1).
  2. Is 8.5 dB package loss applicable for all form factors, including Add-In Card (AIC)/U.2/Enterprise and Data Center SSD Form Factor (EDSFF)? 
    • In the below diagram, the loss budget for a PCIe 5.0 link is broken down into it’s various components. For the PCIe 5.0 specification, the 8.5 dB package loss represents the package loss at the root complex, then there’s a 4.2 dB package loss for the endpoint. Both of these package losses are applicable for CEM (AICs and Systems) devices. At a PCI-SIG Compliance Workshop, U.2 and EDSFF devices are connected to a CEM adapter in order to interface with the CEM compliance test fixtures.


  1. Is there any difference in which order to test Tx and Rx? Do you test Tx or Rx first?
    • The testing order doesn’t matter, but typically Tx is performed first.
  2. What pattern is used for the Rx Link Equalization (LEQ) test?
    • The compliance test pattern is used for the Rx LEQ test (BER test) with any given preset.
  3. Are there any plans to add informational tests for the optional PCIe 5.0 Equalization Bypass feature?
    • No additional tests will be added to the PCIe 5.0 PHY Test Spec. Historically, no additional tests are added to a PCI-SIG compliance test program after the first official compliance workshop, but test vendors have the freedom to add informational measurements to their PCIe testing solutions.
  4. For PCIe 5.0 specification, does the link training still start from PCIe 1.0 specification? Which link speed is the Tx Feedforward Equalizer (FFE) trained in back-channel training?
    • Link training starts from 2.5 GT/s and then trains up to the highest capable speed of the device.
  5. Does Bit Error Rate Testing (BERT) include Protocol Analyzer?
    • The BERT has physical layer measurements as well as PCI Express Link Training LTSSM analysis. The BERT is protocol aware but doesn’t offer the exact same features you would expect from a dedicated protocol analyzer.
  6. When sweeping through presets, is it fine if the device under test (DUT) rejects some of them?
    • For compliance testing, the DUT must be able to transmit Presets P0 through P10. The DUT is required to transmit all presets for the Add-in Card Transmitter Preset Test defined in the PCIe 5.0 PHY Test Specification Section 2.4 and the Add-in Card Transmitter Link Equalization Response Test in Section 2.6.

Retimer/Reference Clock Questions

  1. How does Electrical Compliance testing change if a retimer is on the system? What modes does the retimer need to be in for the Transmitter, Tx Preset and Receiver tests?
    • Compliance testing a retimer device is treated the same as testing a CEM device. There is a retimer test program, but this assumes the retimer will be on a prototype board. If the retimer is on the system (or add-in card), then it just needs to be treated like a system or add-in card. Electrically, it will be the same and the only exposed link is that which is on the connector. The Lane Margining test may need to be run differently, but that is currently under discussion.
  2. Where do we use the " Compliance Receive Rules" and " Enter Compliance Rules" in the case of retimers, because electrical compliance only uses the loopback mode?
    • This would only apply to the Electrical Testing; all Protocol Testing is done in L0 state or non-loopback mode.
  3. Does Spread Spectrum Clocking (SSC) impact compliance tests? If so, how?
    • Protocol Compliance is not affected by SSC; currently, all tests are run with SSC off for protocol. For Electrical Compliance, the Compliance Base Board (CBB) is supplying SSC enabled clock with -0.5% down-spread for the transmitter Signal Quality, Jitter and Preset tests.
  4. Regarding Rx LEQ, does the test include jitter on reference clock (Reflck)?
    • 100 MHz SSC is injected into the DUTs reference clock as defined in the PCIe 5.0 PHY Test Specification section 2.15.6.
  5. Are only common clock tests exercised in the workshop or are they also tested in Separate Reference Clock with Independent Speed (SRIS) or Separate Reference Clock with No Spread Spectrum (SRNS) mode?
    • Common Clock is the most common clock architecture tested at Compliance Workshops, but SRIS and SRNS clock architectures can also be tested. Only one clock mode needs to be tested, which is most often common clock mode.

Register for the Upcoming Compliance Workshop

Member registration is now open for Compliance Workshop #124 taking place on April 24-28 in Burlingame, CA. The workshop will include Integrators List product testing for PCIe 4.0 and PCIe 5.0 products. The registration deadline is Thursday, March 30. Not a member? Join PCI-SIG to participate.