Advanced IP Design for PCI Express® Technology

  • Posted on: 15 November 2022

Advanced IP Design for PCI Express® Technology

By Scott Knowlton, PCI-SIG MWG Co-Chair

As PCI Express® (PCIe®) specifications advance in both bandwidth and complexity, IP (Intellectual Property) vendors need to stay on the cutting edge to develop innovative solutions to keep up with the performance requirements of the latest standards while also having their IP ready before designers begin their product development. With the PCIe 6.0 specification available now and the PCIe 7.0 specification targeted for 2025, the industry demands robust IP solutions to design products that meet the needs of next-generation applications.

This blog will provide a general definition of IP, what IP solutions exist in the marketplace for PCIe specifications and outline the importance of IP for the overall PCIe technology ecosystem.

A General Definition of IP

Essentially, IP provides to the designer a pre-designed functional block. Examples of these functions are libraries, I/Os, Interfaces and Processors. These pre-designed functions are generally delivered as either an RTL netlist (soft IP) or GDSII (hard IP). Utilizing IP allows chip designers to focus on adding differentiating value to their System on a Chip (SoC) design while reducing their time to market and lowering their overall risk. For example, a company designing an AI accelerator, a CPU, or a consumer device would likely want to include support for the PCI Express specification. The IP vendor delivers the required block(s) that are pre-designed to follow the PCIe standard and the designer can focus their efforts on the rest of their design adding value and saving time by not having to design the PCI Express interface. In addition, the IP vendor will have fully tested their IP, taken it to the PCI-SIG compliance workshop and done additional interoperability with other products providing the designer with a low-risk solution.  

PHY, Controller and Verification IP

There are generally two types of design IP that are instantiated in the silicon when it comes to PCIe technology: PHY and Controller IP.  PHY, or physical layer, is the mixed signal physical interface that communicates with the outside world converting the analog signals at the pins into digital form. The Controller IP takes the output data from the PHY and deconstructs the packets down to the actual commands and the data as defined by the PCI Express specification.     

Verification IP is used by designers as part over their overall verification strategy for their SoC device. The Verification IP understands the protocol as defined by the specification and helps the designer drive traffic into the SoC into the PCIe interface and to analyze the data that comes out of the PCI interface. The Verification IP also can include a series of pre-packaged tests to help the designer create more specific scenarios for testing their SoC.

Additionally, the PCI-SIG specifications cover interfaces needed for PCI Express interoperability. Interfaces inside an implementation (e.g., intra-SOC or between chips in a multi-chip implementation) are outside the PCI-SIG scope and governed by non-PCI-SIG specifications like PIPE, AMBA, AXI and more.

PCI Express IP Implementation Challenges

There are multiple challenges in the development of IP for PCI Express. First, the designs of the PHY IP and the Controller IP need to be flexible and configurable to accommodate the continuous expansion of PCI Express technology into different application spaces. As would be expected, the requirements for the PCI Express interface on an SoC for a cell phone, self-driving automobile, server CPU chip and an SSD are all different. They all have different power, performance (lane width, speeds) and area needs. For the Hard PHY IP the complexity expands when supporting differing foundries (TSMC, Samsung, etc.) and technologies i.e., support for 16nm down to 3nm or the transition from NRZ to PAM4 signaling. The IP Vendor has to have a library of ports supporting all of these options. The Digital IP is no different as changes to the PCIe specification to get more throughput may require a new architecture or multiple internal data path widths to meet the bandwidth requirements of the application or additional features like IDE adding complexity. All of these moving parts for the PHY IP and Controller IP need to be optimized to meet the objectives for each of these applications. And, let’s not forget, all of this has to be done while providing backwards compatibility between PCIe specification versions.

Advantages of PCIe IP

Due to the complexities of the PCIe specifications, it no longer makes sense for companies to be creating Hard PHY IP or soft IP for the Controllers that conform to the PCI Express specification and instead focus on what differentiates the product from their competitors.   With pre-designed IP, they can pick the PHY IP and Controller IP that has the right performance for the applications they’re developing.

For companies that want to be on the leading edge, working with an IP vendor provides numerous advantages that can accelerate production of their PCIe products.  Additionally, most IP Vendors will have implemented these interfaces and taken them to one of the PCI-SIG compliance workshops ensuring interoperability with other devices. Utilizing IP reduces the time to market and the overall risk of creating your SoC by using proven IP designs that support the PCI Express specification. Rather than doing it on their own, companies can benefit from buying IP then spending their time on the rest of their architecture, which is what really differentiates them from their competitors.

Learn more about PCIe Specifications

If you want to learn more about the technical details of the PCIe specifications, review the FAQ. For a list of all PCI-SIG member companies, including IP vendors, view the Member List.