PCI-SIG specifications define standards driving the industry-wide compatibility of peripheral component interconnects. Members regularly review them, providing commentary and change requests when necessary. These requests are considered by technical workgroups and applied as appropriate, resulting in collaboratively devised specifications benefiting millions of platforms and add-in devices.
Engineering Change Request Process
PCI-SIG members may submit requests to change specifications here. The Engineering Change Request process and form can be found here.
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PCI-SIG members may access specifications online, at no cost, using the Specification Library. Members may filter their search by technology type, revision, and the type of document. Select the appropriate filters and then select the Filter button to initiate your search. Alternatively, members may purchase a hard copy of the specifications, at a reduced member rate, here.
Non-members who are interested in purchasing specifications may submit their order here.
PCI Code & ID Assignment Specifications
The PCI Code & ID Assignment Specifications are accessible to non-members without charge here. PCI-SIG members can download these specifications directly from the Specifications Library below.
This ECN defines a _DSM interface for the OS to lear...view moreThis ECN defines a _DSM interface for the OS to learn whether the platform supports generation of synchronous processor exceptions. If firmware has granted the OS control of the DPC Capability (see _OSC Control[7]) and the platform supports generation of synchronous processor exceptions for an RP PIO error type, the OS may set the corresponding RP PIO Exception bit. If the OS does not have control of the DPC Capability, it may read the RP PIO Exception Register to learn how the platform will report RP PIO errors.
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Update the PCI Firmware Specification to remove offe...view moreUpdate the PCI Firmware Specification to remove offensive terms and adopt inclusive language. This follows a similar update that was implemented in the PCI Base specification.
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This ECN extends the functionality provided by the T...view moreThis ECN extends the functionality provided by the TPH Features _DSM introduced in Revision 3.3 of the PCI Firmware Specification.
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This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.
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This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.
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Changes are requested to be made to Section 4.5.1, _...view moreChanges are requested to be made to Section 4.5.1, _OSC Interface for PCI Host Bridge Devices and Section 4.5.2.4 Dependencies Between _OSC Control Bits. The changes will enable the Operating System and system firmware to negotiate ownership of the System Firmware Intermediary (SFI) Extended Capability Structure.
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Since the 3.2 release of the Firmware Specification,...view moreSince the 3.2 release of the Firmware Specification, several ECRs have been submitted which add _DSM functions or modify existing Functions. The Revision value for each added/modified Function has been included in each ECR, but the value has been applied in a manner inconsistent with previous revisions of the Specification.
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This ECN adds new capabilities by way of adding new ...view moreThis ECN adds new capabilities by way of adding new Device Specific Method (_DSM) to the PCI Firmware Spec.
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Changes are requested to clarify Section 4.6.5....view moreChanges are requested to clarify Section 4.6.5. There is a lot of confusion about where the _DSM object should be located and what the function 5 means. This change Notice proposes no functional changes.
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This ECN is based on the TLP Processing Hint (TPH) o...view moreThis ECN is based on the TLP Processing Hint (TPH) optional capability. The Steering Tag (ST) field handling is platform specific, and this ECN provides a model for how a device driver can determine if the platform root complex supports decode of Steering Tags for specific vendor handling.
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Changes are requested to be made to Section 4.5.1, _...view moreChanges are requested to be made to Section 4.5.1, _OSC Interface for PCI Host Bridge Devices and Section 4.5.2.4 Dependencies Between _OSC Control Bits. The changes will enable the Operating System to advertise if it is capable of support _HPX PCI Express Descriptor Setting Record (Type 3) to the firmware. It also enables the Operating System and the Firmware to negotiate ownership of the PCIe Completion Timeout registers.
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The changes effect the PCI Firmware Specification, R...view moreThe changes effect the PCI Firmware Specification, Revision 3.2 and will enable the Operating System to advertise its Downstream Port containment related capabilities to the firmware. It also enables the Operating System and the Firmware to negotiate ownership of Downstream Port Containment extended capability register block and collaboratively manage Downstream Port Containment events.
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The changes affect the PCI Firmware Specification, R...view moreThe changes affect the PCI Firmware Specification, Revision 3.2 and enable the MCFG table format to allow for multiple memory mapped base address entries, instances of Table 4-3, per single PCI Segment Group.
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This ECN adds two capabilities by way of adding func...view moreThis ECN adds two capabilities by way of adding functions to the PCI Firmware Spec defined _DSM definition.
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This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.
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This ECN affects the PCI Firmware Specification v3.1...view moreThis ECN affects the PCI Firmware Specification v3.1 and allows certain errors to be suppressed by platform if software stack ensured error containment. Also removes the implementation note in section 4.5.2.4 which is not representative of OS behavior.
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This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI™, PCI-X, and PCI Express® systems in a host computer.
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A number of PCIe base specifications ECNs have been ...view moreA number of PCIe base specifications ECNs have been approved that require software support. In some cases, platform firmware needs to know if the OS running supports certain features, or the OS needs to be able to request control of certain features from platform firmware. In other cases, the OS needs to know information about the platform that cannot be discovered through PCI enumeration, and ACPI must be used to supply the additional information.
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This ECN rectifies the differences between the DMTF ...view moreThis ECN rectifies the differences between the DMTF SM CLP Specification and its supporting documents with the current PCI Firmware 3.0 Specification. Also, it clarifies the supporting documents required for successfully implementing CLP in an X86 PCI FW 3.0 compatible option ROM.
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This ECN attempts to make clarifications such that t...view moreThis ECN attempts to make clarifications such that the system firmware and multiple operating systems can have the same interpretation of the specification and work interoperably.
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This ECN adds a function to the _DSM Definitions for...view moreThis ECN adds a function to the _DSM Definitions for PCI to provide an indication to an operating system that it can ignore the PCI boot configuration setup by the firmware during system initialization.
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This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.
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This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.
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This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.
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The changes are to Socket-1, Keys E and A-E...view more
The changes are to Socket-1, Keys E and A-E
Addition of 1.8V IO support type (1 pin)
Addition of 1.8V IO Voltage source (1 pin)
Addition of WI-FI_DISABLE and BT_DISABLE signals overlaid onto W_DISABLE1#, W_DISABLE2#
Additional antenna assignment which allows for multiple Bluetooth antennas.
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This proposal introduces an additional width, compon...view moreThis proposal introduces an additional width, component heights, and the ability to specify the top surface as a planar.
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This is a companion specification to the PCI Express...view moreThis is a companion specification to the PCI Express Base Specification. The primary focus of this specification is the implementation of cabled PCI Express®. No assumptions are made regarding the implementation of PCI Express-compliant Subsystems on either side of the cabled Link (PCI Express Card Electromechanical (CEM), ExpressCard™, ExpressModule™, PXI Express™, or any other form factor). Such form factors are covered in separate specifications
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Revision A (March 4, 2020) corrects an oversight in ...view moreRevision A (March 4, 2020) corrects an oversight in the original revision (November 28, 2018). The Socket 2 Key B PCIe/USB3.1 Gen1-based WWAN Adapter Pinout was not updated to reflect the addition of 1.8V sideband support like the other tables. The affected portion is highlighted in Table 33 Socket 2 Key B PCIe/USB3.1 Gen1-based WWAN Adapter Pinout.
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This is a companion specification to the PCI Exp...view moreThis is a companion specification to the PCI Express Base Specification. The primary focus of this specification is the implementation of cabled PCI Express®. No assumptions are made regarding the implementation of PCI Express-compliant Subsystems on either side of the cabled Link (PCI Express Card Electromechanical (CEM), ExpressCard™, ExpressModule™, PXI Express™, or any other form factor). Such form factors are covered in separate specifications.
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The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution.
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This proposal introduces 8GT/s electrical compliance...view moreThis proposal introduces 8GT/s electrical compliance details for M.2 based SSDs.
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This proposal repurposes five RFU pins in the 16 mm ...view moreThis proposal repurposes five RFU pins in the 16 mm x 20 mm BGA ball map to be optionally used for indicating PWR1, PWR2, and PWR3 supply voltage requirements to the Platform.
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This is a modification of the cable assembly memory ...view moreThis is a modification of the cable assembly memory map defined in the OCuLink Memory Map ECN. Some bits contained within the external cable assembly's memory are modified to allow for cable aggregation.
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This is a modification of the cable assembly memory ...view moreThis is a modification of the cable assembly memory map defined in the OCuLink Memory Map ECN. Some bits contained within the external cable assembly's memory are modified to allow for cable aggregation.
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High Volume Manufacturing (HVM) benefits from the ab...view moreHigh Volume Manufacturing (HVM) benefits from the ability to set manufacturing specific SFF8639 Module modes that enable multiplexing of standard connector pins for manufacturing test specific use. This ECR is to define a method to allow the Host to enable Manufacturing Mode on the SFF-8639 Module through the standard interface connector. The Manufacturing Mode solution proposed is consistent with that already approved in SNIA SFFTA-1001 Revision 1.1 for SFF-8639 use.
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Changes are requested to be made to Section 4.5.1, _...view moreChanges are requested to be made to Section 4.5.1, _OSC Interface for PCI Host Bridge Devices and Section 4.5.2.4 Dependencies Between _OSC Control Bits. The changes will enable the Operating System to advertise if it is capable of support _HPX PCI Express Descriptor Setting Record (Type 3) to the firmware. It also enables the Operating System and the Firmware to negotiate ownership of the PCIe Completion Timeout registers.
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The changes effect the PCI Firmware Specification, R...view moreThe changes effect the PCI Firmware Specification, Revision 3.2 and will enable the Operating System to advertise its Downstream Port containment related capabilities to the firmware. It also enables the Operating System and the Firmware to negotiate ownership of Downstream Port Containment extended capability register block and collaboratively manage Downstream Port Containment events.
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The changes affect the PCI Firmware Specification, R...view moreThe changes affect the PCI Firmware Specification, Revision 3.2 and enable the MCFG table format to allow for multiple memory mapped base address entries, instances of Table 4-3, per single PCI Segment Group.
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The focus of this specification is on PCI Express (P...view moreThe focus of this specification is on PCI Express (PCIe®) solutions utilizing the SFF-8639 connector interface. Form factors include, but are not limited to, those described in the SFF-8201 Form Factor Drive Dimensions Specification. Other form factors, such as PCI Express CEM are documented in other independent specifications.
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Final Release against Base Revision 3.1a.Subsequent ...view moreFinal Release against Base Revision 3.1a.Subsequent Errata will be against Base Revision 4.0
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This ECN adds two capabilities by way of adding func...view moreThis ECN adds two capabilities by way of adding functions to the PCI Firmware Spec defined _DSM definition.
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Defines mechanisms for simple storage enclosure mana...view moreDefines mechanisms for simple storage enclosure management for NVMe SSDs, consistent with established capabilities in the storage ecosystem, with the first version of this capability defining a register interface for LED control. This ECN defines a new PCI Express extended capability called Native PCIe Enclosure Management (NPEM).
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This ECN specifies changes to the PCI Local Bus Spec...view moreThis ECN specifies changes to the PCI Local Bus Specification Revision 3.0 and the PCI Express CEM Specification 3.0. Changes to the PCI Local Bus Specification cover a new VPD encoding and a 32-bit field. Changes to the PCI Express CEM Specification cover a series of graphs used to classify air flow impedance and thermal properties under varying conditions as well as the test figure and process to create these graphs for a given adapter add-in card.
Adapter add-in card types supported by this include all SINGLE-SLOT and DUAL-SLOT PCIe CEM adapter add-in cards without integrated air movers, including standard height adapter add-in cards as well as low-profile adapter add-in cards). Adapter add-in cards with an integrated air mover were not addressed due to the added complication of their integrated air mover in the overall platform’s potential cooling redundancy.
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Defines a new, optional PCI-SIG Defined Type 1 Vendo...view moreDefines a new, optional PCI-SIG Defined Type 1 Vendor Defined Message.
This message provides software and/or firmware, running on a Function, additional information to uniquely identify that Function, within a large system or a collection of systems.
When a single system contains multiple PCI Express Hierarchies, this message tells a Function which Hierarchy it resides in. This value, in conjunction with the Routing ID number uniquely identifies a Function within that system.
In clustered system, this message can include a System Globally Unique Identifier (System GUID) for each system. This value, in conjunction with the Hierarchy ID and Routing ID uniquely identifies a Function within that cluster.
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This ECR is intended to address a class of issues wi...view moreThis ECR is intended to address a class of issues with PCI/PCIe architecture that relate to resource allocation inefficiency. To explain this, first we must define some terms:
Static use cases, refer to scenarios where resources are allocated at system boot and then typically not changed again
Dynamic use cases, refer to scenarios where run-time resource rebalancing (allocation of new resources, freeing of resources no longer needed) is required, due to hot add/remove, or by other needs.
In the Static cases there are limits on the size of hierarchies and number of Endpoints due to the Bus & Device Number “waste” caused by the PCI/PCIe architectural definition for Switches, and by the requirement that Downstream Ports associate an entire Bus Number with their Link. This proposal addresses this class of problems by “flattening” the use of Routing IDs so that Switches and Downstream Ports are able to make more efficient use of the available space.
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Similar to, and based on, the Resizable BAR and Expa...view moreSimilar to, and based on, the Resizable BAR and Expanded Resizable BAR ECNs, this optional ECN adds a capability for PFs to be able to resize their VF BARs. This ECN is written with the expectation that the Expanded Resizable BAR ECN will have been released prior to this ECN’s release. This ECN supports all of the BAR sizes defined by both the Resizable BAR and Expanded Resizable BAR ECNs.
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Update SR-IOV specification to reflect current PCI C...view moreUpdate SR-IOV specification to reflect current PCI Code and ID Assignment Specification, regarding PCI capabilities and PCI-E extended capabilities. Clarify the requirements for VFs regarding the other Capabilities added by ECNs that should have updated the SR-IOV specification but did not.
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MSI is enhanced to include an Extended Message Data ...view moreMSI is enhanced to include an Extended Message Data Field for the function generating the interrupt. The MSI Capability Structure is modified to enable the new feature to be enabled/disabled; and a new Extended Message Data Field to be configured. This change only applies to MSI and not MSI-X.
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The Resizable BAR capability currently allows BARs o...view moreThe Resizable BAR capability currently allows BARs of up to 512 GB (239), which allows address bits <38:0> to be passed into an Endpoint. This proposal extends resizable BARs to up to 263 bits, which supports the entire address space.
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Definition of electrical eye limits (Eye Height and ...view moreDefinition of electrical eye limits (Eye Height and Eye Width) at the M.2 connector for SSIC host and device transmitter is proposed to be added in the specification.
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This ECN implements a variety of spec modifications ...view moreThis ECN implements a variety of spec modifications intended to correct inconsistencies related to, and to support more consistent implementation of, Root Complex integrated Endpoints, with a particular focus on issues relating to Single Root IO Virtualization (SR-IOV).
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This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
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This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
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This ECN defines two sets of related changes to supp...view moreThis ECN defines two sets of related changes to support an Emergency Power Reduction mechanism and to provide software visibility for this mechanism:
1. The Card Electromechanical Specification is updated to define an optional Emergency Power Reduction mechanism using RSVD pin B30.
2. The PCI Express Base Specification is updated to define an optional mechanism to indicate support for Emergency Power Reduction and to provide visibility as to the power reduction status of a Device.
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Define a Vendor-Specific Extended Capability that is...view moreDefine a Vendor-Specific Extended Capability that is not tied to the Vendor ID of the Component 5 or Function. This capability includes a Vendor ID that determines the interpretation of the remainder of the capability. It is otherwise similar to the existing Vendor-Specific Extended Capability.
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This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express systems in a host computer.
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Provide specification for Physical Layer protocol aw...view moreProvide specification for Physical Layer protocol aware Retimers for PCI Express 3.0/3.1.
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Modifies specifications to provide revised JTOL curv...view moreModifies specifications to provide revised JTOL curve for SRIS mode and provides additional frequency domain constraint of SSC profile jitter on reference clocks.
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Modifies the limits used by the PLL bandwidth test t...view moreModifies the limits used by the PLL bandwidth test to allow guardband for a single PLL test solution to be used at PCI-SIG compliance workshops without impacting pass/fail results for member companies.
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This ECN affects the PCI Firmware Specification v3.1...view moreThis ECN affects the PCI Firmware Specification v3.1 and allows certain errors to be suppressed by platform if software stack ensured error containment. Also removes the implementation note in section 4.5.2.4 which is not representative of OS behavior.
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Defines mechanisms to reduce the time software need...view more Defines mechanisms to reduce the time software needs to wait before issuing a Configuration Request to a PCIe Function or RC-integrated PCI Function following power on, reset, or power state transitions.
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This specification is a companion for the PCI Expres...view moreThis specification is a companion for the PCI Express Base Specification, Revision 3.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications. Access Test Channel S-Parameters.
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This test specification primarily covers tests of PC...view moreThis test specification primarily covers tests of PCI Express platform firmware for features critical to PCI Express. This specification does not include the complete set of tests for a PCI Express System.
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This document primarily covers PCI Express testing o...view moreThis document primarily covers PCI Express testing of all defined PCI Express Device Types and RCRBs for the standard Configuration Space mechanisms, registers, and features in Chapter 6 of the PCI Local Bus Specification and Chapter 7 of the PCI Express Base Specification (some additional tested registers are described in other specifications that are referenced in the individual test description).
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This test specification primarily covers testing of ...view moreThis test specification primarily covers testing of PCI Express Device and Port types for compliance with the link layer and transaction layer requirements of the PCI Express Base Specification. Device and Port types that do not have a link (e.g., Root Complex Integrated Endpoints, Root Complex Event Collectors) are not tested under this test specification. At this point, this test specification does not describe the full set of PCI Express tests for all link layer or transaction layer requirements.
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This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building add-in cards or system boards to the PCI Express Card Electromechanical Specification 3.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.
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This ECR defines an optional mechanism, that establ...view more This ECR defines an optional mechanism, that establishes, depending on implementation, one or more substates of the L1 Link state, which allow for dramatically lower idle power, including near complete removal of power for high speed circuits.
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This ECR defines a new logical layer mapping of PCI ...view moreThis ECR defines a new logical layer mapping of PCI Express over the MIPI Alliance M-PHY1 specification.
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Defines an optional-normative Precision Time Measure...view moreDefines an optional-normative Precision Time Measurement (PTM) capability. To accomplish this, Precision Time Measurement defines a new protocol of timing measurement/synchronization messages and a new capability structure.
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Provide specifications to enable separate Refclk wit...view moreProvide specifications to enable separate Refclk with Independent Spread Spectrum Clocking (SSC) architecture.
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The PCI Express 3.0 describes a method to simulate 8...view moreThe PCI Express 3.0 describes a method to simulate 8GT/s channel compliance using a statistical data eye simulator. To help members perform this simulation, a free open source tool called Seasim is provided below. This tool has been tested by members of the Electrical Working Group on multiple channels and has reached version 0.54 which should be useful for members designing 8GT/s systems.
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Change the Sub-Class assignment for Root Complex Eve...view moreChange the Sub-Class assignment for Root Complex Event Collector from 06h to 07h.
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This optional normative ECN defines enhancements to ...view moreThis optional normative ECN defines enhancements to the Downstream Port Containment (DPC) ECN, an ECN that enabled automatic disabling of the Link below a Downstream Port following an uncorrectable error. The DPC ECN defined functionality for both Switch Downstream Ports and Root Ports. This ECN mostly defines functionality that is specific to Root Ports, functionality referred to as “RP Extensions for DPC”.
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This ECN defines a new error containment mechanism f...view moreThis ECN defines a new error containment mechanism for Downstream Ports as well as minor enhancements that improve asynchronous card removal. Downstream Port Containment (DPC) is the automatic disabling of the Link below a Downstream Port following an uncorrectable error. This prevents the potential spread of data corruption (all TLPs subsequent to the error are prevented from propagating either Upstream or Downstream) and enables error recovery if supported by software.
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This optional normative ECN defines a simple protoco...view moreThis optional normative ECN defines a simple protocol where a device can register interest in one or more cachelines in host memory, and later be notified via a hardware mechanism when any registered cachelines are updated.
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Receivers that operate at 8.0 GT/s with an impedance...view moreReceivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the following LTSSM states: Polling, Rx_L0s, L1, L2, and Disabled.
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This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI™, PCI-X, and PCI Express® systems in a host computer.
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This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
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This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
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This involves a minor upward compatible change in Ch...view moreThis involves a minor upward compatible change in Chapter 3, Chapter 4 and a new Appendix T.
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This change allows for all Root Ports with the End-...view more This change allows for all Root Ports with the End-End TLP Prefix Supported bit Set to have different values for the Max End-End TLP Prefixes field in the Device Capabilities 2 register. It also changes and clarifies error handling for a Root Port receiving a TLP with more End-End TLP Prefixes than it supports.
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A number of PCIe base specifications ECNs have been ...view moreA number of PCIe base specifications ECNs have been approved that require software support. In some cases, platform firmware needs to know if the OS running supports certain features, or the OS needs to be able to request control of certain features from platform firmware. In other cases, the OS needs to know information about the platform that cannot be discovered through PCI enumeration, and ACPI must be used to supply the additional information.
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This ECN rectifies the differences between the DMTF ...view moreThis ECN rectifies the differences between the DMTF SM CLP Specification and its supporting documents with the current PCI Firmware 3.0 Specification. Also, it clarifies the supporting documents required for successfully implementing CLP in an X86 PCI FW 3.0 compatible option ROM.
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This ECN attempts to make clarifications such that t...view moreThis ECN attempts to make clarifications such that the system firmware and multiple operating systems can have the same interpretation of the specification and work interoperably.
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This ECN adds a function to the _DSM Definitions for...view moreThis ECN adds a function to the _DSM Definitions for PCI to provide an indication to an operating system that it can ignore the PCI boot configuration setup by the firmware during system initialization.
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This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.
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This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.
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This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.
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Changes are requested to be made to Section 4.5.1, _...view moreChanges are requested to be made to Section 4.5.1, _OSC Interface for PCI Host Bridge Devices and Section 4.5.2.4 Dependencies Between _OSC Control Bits. The changes will enable the Operating System to advertise if it is capable of support _HPX PCI Express Descriptor Setting Record (Type 3) to the firmware. It also enables the Operating System and the Firmware to negotiate ownership of the PCIe Completion Timeout registers.
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The changes effect the PCI Firmware Specification, R...view moreThe changes effect the PCI Firmware Specification, Revision 3.2 and will enable the Operating System to advertise its Downstream Port containment related capabilities to the firmware. It also enables the Operating System and the Firmware to negotiate ownership of Downstream Port Containment extended capability register block and collaboratively manage Downstream Port Containment events.
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The changes affect the PCI Firmware Specification, R...view moreThe changes affect the PCI Firmware Specification, Revision 3.2 and enable the MCFG table format to allow for multiple memory mapped base address entries, instances of Table 4-3, per single PCI Segment Group.
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This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.
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Enhanced Allocation is an optional Conventional PCI ...view moreEnhanced Allocation is an optional Conventional PCI Capability that may be implemented by Functions to indicate fixed (non reprogrammable) I/O and memory ranges assigned to the Function, as well as supporting new resource “type” definitions and future extensibility to also support reprogrammable allocations.
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This ECR provides two additional ACPI DSM functions ...view moreThis ECR provides two additional ACPI DSM functions to inform OS about the possible time reduction opportunities:
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This ECN affects the PCI Firmware Specification v3.1...view moreThis ECN affects the PCI Firmware Specification v3.1 and allows certain errors to be suppressed by platform if software stack ensured error containment. Also removes the implementation note in section 4.5.2.4 which is not representative of OS behavior.
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Update the references to the latest UEFI Specificati...view moreUpdate the references to the latest UEFI Specification. Make clarifications in 5.1.2 that the pointers to the Device List, the Configuration Utility Code header and the DMTF CLP Entry Point are not applicable to the UEFI Option ROMs.
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This ECN updates the subclass ID description in the ...view moreThis ECN updates the subclass ID description in the Class Code & Capability ID Specification.
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This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI™, PCI-X, and PCI Express® systems in a host computer.
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This ECN extracts the Class Code definitions from Ap...view moreThis ECN extracts the Class Code definitions from Appendix D and the Capability ID definitions from Appendix H, for consolidation into a new standalone document that’s easier to maintain. The new document will also consolidate Extended Capability definitions from the PCIe Base spec and various other PCIe specs.
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This ECR proposes a mechanism (new extension to _DSM...view moreThis ECR proposes a mechanism (new extension to _DSM) to make the device names/labels under Operating Systems deterministic. Currently, there is no well defined mechanism to consistently associate platform specific device names and instances of a device type under operating system. As a result, instance labels for specific device types under various operating systems (ex: ethx label for networking device instance under Linux OS) do not always map into the platform designated device labels. Additionally, the instance labels can change based on the system configuration. For example, under Linux operating systems, the “eth0” label does not necessarily map to the first embedded networking device as designed in a given platform. Depending on the hardware bus topology, current configuration including the number and type of networking adapters installed, the eth0 label assignment could change in a given platform.
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A number of PCIe base specifications ECNs have been ...view moreA number of PCIe base specifications ECNs have been approved that require software support. In some cases, platform firmware needs to know if the OS running supports certain features, or the OS needs to be able to request control of certain features from platform firmware. In other cases, the OS needs to know information about the platform that cannot be discovered through PCI enumeration, and ACPI must be used to supply the additional information.
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This update references to sections in the DMTF Serve...view moreThis update references to sections in the DMTF Server Management Command Line Protocol (SM CLP) Specification (DSP0214) to match the most recent version SM CLP Specification (v1.0.2). It also clarifies that the references to the DMTF SM CLP specification are referencing v1.0.2. and adds a reference to the DMTF SM CLP specification in section 1.2 Reference Documents.
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This is a request to update the UEFI PCI Services....view moreThis is a request to update the UEFI PCI Services. No functional changes. In the case of the UGA reference, UGA has been obsolete by the UEFI Specification and is replaced by the new GOP.
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This ECN allows the unoccupied slots' power to be of...view moreThis ECN allows the unoccupied slots' power to be off at hand-off, which is a reasonable implementation and many systems implement that way today.
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This ECN rectifies the differences between the DMTF ...view moreThis ECN rectifies the differences between the DMTF SM CLP Specification and its supporting documents with the current PCI Firmware 3.0 Specification. Also, it clarifies the supporting documents required for successfully implementing CLP in an X86 PCI FW 3.0 compatible option ROM.
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For conventional PCI devices integrated into a PCI E...view moreFor conventional PCI devices integrated into a PCI Express Root Complex, this defines an optional capability structure that includes selected advanced features originally defined for PCI Express. This capability is intended to be extensible in the future. For the initial definition, the Transactions Pending (TP) and Function Level Reset (FLR) are included.
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This ECN attempts to make clarifications such that t...view moreThis ECN attempts to make clarifications such that the system firmware and multiple operating systems can have the same interpretation of the specification and work interoperably.
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This ECN adds a function to the _DSM Definitions for...view moreThis ECN adds a function to the _DSM Definitions for PCI to provide an indication to an operating system that it can ignore the PCI boot configuration setup by the firmware during system initialization.
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This document describes the hardware independent fir...view moreThis document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.
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The functional changes proposed involve the definiti...view moreThe functional changes proposed involve the definition of a new Capabilities List ID (and associated Capability register set). This new Capabilities ID will identify to system firmware (BIOS/OROM), a Serial ATA (SATA) host bus adapter’s (HBA) support of optional features that may be defined in the particular SATA HBA specification (i.e. Advanced Host Controller Interface - AHCI).
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This document contains the formal specifications of the protocol, electrical, and mechanical features of the PCI Local Bus Specification, Revision 3.0, as the production version effective February 3, 2004. The PCI Local Bus Specification, Revision 2.3, issued March 29, 2002, is not superseded by this specification.
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This document contains the formal specifications of ...view moreThis document contains the formal specifications of the protocol, electrical, and mechanical features of the PCI Local Bus Specification, Revision 3.0, as the production version effective February 3, 2004. The PCI Local Bus Specification, Revision 2.3, issued March 29, 2002, is not superseded by this specification.
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Create a new class code for SerialATA host-based ada...view moreCreate a new class code for SerialATA host-based adapters (HBAs) that can be identified by system software. The new class code will allow for system software to identify a controller as being attached to serial ATA devices and serial attached SCSI devices. This will help system software load drivers that may be specific to these interfaces.
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Extend the current MSI functionality to support a la...view moreExtend the current MSI functionality to support a larger number of MSI vectors, plus a separate and independent Message Address and Message Data for each MSI vector. Allow more flexibility when SW allocates fewer MSI vectors than requested by HW. Enable per-vector masking capability.
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The intent of this ECR is to update the PCI base spe...view moreThe intent of this ECR is to update the PCI base specifications to include PCI connector metallurgical practices which have been commonly accepted or introduced since the original wording was drafted before the PCI 2.0 specification. With an overwhelming majority of PCI and PCI-X connectors shipped in the world that do not meet the PCI specification for contact finish plating, the most efficient way to rectify the situation is to correct the specification.
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