Specifications

Technology: PCI Express
Specification Title Spec Rev Document Type Release Date
WWAN Key C Definition

This ECR describes the necessary changes to enable a new WWAN Key C definition to be included as an addition to the existing spec. The intent is to create a dedicated WWAN socket Key and pinout definition. This new pinout definition will be focused on WWAN specific interfaces and needs. 

1.x ECN
PCI Code and Assignment Specification Revision 1.6

This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications.

1.x Specification
PCI Code and Assignment Specification Revision 1.6 with Change Bar

This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications.

1.x Specification
M.2 2242 WWAN Module

Add 2242 form factor for WWAN modules using Socket 2 with key B.

1.x ECN
Errata for the PCI Express Base Specification Revision 3.0 3.x Errata
Power-up requirements for PCIe side bands in a Vbat powered system

In ECN “Power-up requirements for PCIe side bands (PERST#, etc.)” - submitted by Dave Landsman and Ramdas Kachare - section 3.1.3.2.1 is redefined to provide a more realistic timing model for reset.

1.x ECN
Tx Blanking and SYSCLK on Socket 1 Related Pinouts

The proposed change is to include 2 GNSS Aiding signals, that we already have allocated in the Type 1216 pinout, to the Socket 1 Key E pinout and Type 2226/3026 pinout. Due to lack of free pins in the Key E pinout, it is proposed to define 2 SDIO Input signals as dual functional pins. They would be defined with their original SDIO functionality along with and alternate GNSS Aiding signals functionality to enable a GNSS solution on Type 2230 solutions on Socket 1 Key E solutions. The GNSS signals to be added are the Tx Blanking and SYSCLK signals and it is suggested to overlay them on the SDIO RESET# and SDIO CLK respectively which are also inputs. In this way it is less likely to cause a potential contention. 

1.x ECN
M.2 COEX Signal Definition - UART

Definition of two of the three COEX pins as a UART Tx/Rx communication path between Socket 1 and Socket 2 in favor of WWAN ßà Connectivity coexistence. The intent is to definitively define the location of the source and sink sides of the signal path. 

1.x ECN
Transition of NFC Signals from 3.3V to 1.8V

The proposed change is to change the current voltage level of the NFC related signals (I2C DATA, I2C CLK and ALERT#) on the Connectivity pinouts and definitions from 3.3V to 1.8V signal level to better align with future platforms operating signal levels typical in the industry. 

1.x ECN
PCI Express Base Specification Revision 3.1 with Change Bar

This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. 

3.x Specification
PCI Express Base Specification Revision 3.1

This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. 

3.x Specification
Extension Devices

Provide specification for Physical Layer protocol aware Retimers for PCI Express 3.0/3.1.

3.x ECN
Power-up requirements for PCIe side bands (PERST#, etc.)

Section 3.1.3.2.1 is redefined to provide a more realistic timing model for reset.

1.x ECN
M.2 Signal Definition – Audio & ANTCTL Functions

Definition of the four Audio pins to provide definitive functions assigned to each pin of the Audio interface.

1.x ECN
SMBus interface for SSD Socket 2 and Socket 3

SMBus interface signals are included in sections 3.2 and 3.3 and related minor clarifications added to sections 1.2, 1.3, 2.2, 4.1, 4.2, 5.2.2, and 5.3.

1.x ECN
Add USB 3.0 to the Mini Card

Mobile broadband peak data rates continue to increase. With LTE category 5, USB 2.0 will not meet the performance requirements. LTE category 5 peak data rates are 320 Mbps downlink; 75 Mbps uplink. Most USB 2.0 implementations achieve a maximum of about 240 Mbps throughput. Looking longer term, the ITU has set a target of 1 Gbits/s for low mobility applications for IMT Advanced.

2.x ECN
NOP DLLP

This ECN accomplishes two housekeeping tasks associated with DLLP encoding.

3.x ECN
Separate Refclk Independent SSC Architecture (SRIS) JTOL and SSC Profile Requirements

Modifies specifications to provide revised JTOL curve for SRIS mode and provides additional frequency domain constraint of SSC profile jitter on reference clocks.

3.x ECN
PCI Code and Assignment Specification Revision 1.5

This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications.

1.x Specification
PCI Code and Assignment Specification Revision 1.5 with Change Bar

This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications.

1.x Specification
Tighten Mini Card Power Rail Voltage Tolerance

Modify the Mini Card specification to tighten the power rail voltage tolerance.

2.x ECN
PLL Bandwidth Test Limits

Modifies the limits used by the PLL bandwidth test to allow guardband for a single PLL test solution to be used at PCI-SIG compliance workshops without impacting pass/fail results for member companies.

3.x ECN
PCI Express M.2 Specification Revision 1.0

The M.2 form factor is used for Mobile Add-In cards. The M.2 is a natural transition from the Mini Card and Half-Mini Card to a smaller form factor in both size and volume. The M.2 is a family of form factors that will enable expansion, contraction, and higher integration of functions onto a single form factor module solution.

1.x Specification
PCI Code and Assignment Specification Revision 1.4

This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications.

1.x Specification
PCI Code and Assignment Specification Revision 1.4 with Change Bar

This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications.

1.x Specification
Readiness Notifications (RN)

 Defines mechanisms to reduce the time software needs to wait before issuing a Configuration Request to a PCIe Function or RC-integrated PCI Function following power on, reset, or power state transitions.

3.x ECN
PCI Express Card Electromechanical Specification Revision 3.0

This specification is a companion for the PCI Express Base Specification, Revision 3.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications.

3.x Specification
PCI Express Architecture Platform Init/Config Revision 3.0

This test specification primarily covers tests of PCI Express platform firmware for features critical to PCI Express. This specification does not include the complete set of tests for a PCI Express System.

3.x Specification
PCI Express Architecture PHY Test Specification Revision 3.0

This document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building add-in cards or system boards to the PCI Express Card Electromechanical Specification 3.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.

3.x Specification
PCI Express Architecture Configuration Space Test Specification Revision 3.0

This document primarily covers PCI Express testing of all defined PCI Express Device Types and RCRBs for the standard Configuration Space mechanisms, registers, and features in Chapter 6 of the PCI Local Bus Specification and Chapter 7 of the PCI Express Base Specification (some additional tested registers are described in other specifications that are referenced in the individual test description).

3.x Specification
PCI Express® Architecture Link Layer and Transaction Layer Test Specification Revision 3.0

This test specification primarily covers testing of PCI Express Device and Port types for compliance with the link layer and transaction layer requirements of the PCI Express Base Specification. Device and Port types that do not have a link (e.g., Root Complex Integrated Endpoints, Root Complex Event Collectors) are not tested under this test specification. At this point, this test specification does not describe the full set of PCI Express tests for all link layer or transaction layer requirements.

3.x Specification
L1 PM Substates with CLKREQ, Revision 1.0a

 This ECR defines an optional mechanism, that establishes, depending on implementation, one or more substates of the L1 Link state, which allow for dramatically lower idle power, including near complete removal of power for high speed circuits.

3.x ECN
M-PCIe

This ECR defines a new logical layer mapping of PCI Express over the MIPI Alliance M-PHY1 specification.

3.x ECN
Precision Time Measurement (PTM), Revision 1.0a

Defines an optional-normative Precision Time Measurement (PTM) capability. To accomplish this, Precision Time Measurement defines a new protocol of timing measurement/synchronization messages and a new capability structure.

3.x ECN
Separate Refclk Independent SSC Architecture (SRIS)

Provide specifications to enable separate Refclk with Independent Spread Spectrum Clocking (SSC) architecture.

3.x ECN
Seasim Software Package

The PCI Express 3.0 describes a method to simulate 8GT/s channel compliance using a statistical data eye simulator. To help members perform this simulation, a free open source tool called Seasim is provided below. This tool has been tested by members of the Electrical Working Group on multiple channels and has reached version 0.54 which should be useful for members designing 8GT/s systems.
 

3.x Specification
Change Root Complex Event Collector Class Code

Change the Sub-Class assignment for Root Complex Event Collector from 06h to 07h.

3.x ECN
Enhanced DPC (eDPC)

This optional normative ECN defines enhancements to the Downstream Port Containment (DPC) ECN, an ECN that enabled automatic disabling of the Link below a Downstream Port following an uncorrectable error. The DPC ECN defined functionality for both Switch Downstream Ports and Root Ports. This ECN mostly defines functionality that is specific to Root Ports, functionality referred to as “RP Extensions for DPC”.

3.x ECN
PCI Express Architecture Configuration Space Test Specification Revision 2.0a

This document primarily covers PCI Express testing of root complexes, switches, bridges, and endpoints for the standard configuration mechanisms, registers, and features in Chapter 7 of the PCI Express Base Specification, Revision 2.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.

2.x Specification
PCI Express Architecture Configuration Space Test Specification Revision 2.0a with Change Bar

This document primarily covers PCI Express testing of root complexes, switches, bridges, and endpoints for the standard configuration mechanisms, registers, and features in Chapter 7 of the PCI Express Base Specification, Revision 2.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.

2.x Specification
PCI Express Architecture PHY Test Specification Revision 2.0

This document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building add-in cards or system boards to the PCI Express Card Electromechanical Specification, Revision 2.0. This specification does not describe the full set of PCI Express tests and assertions for these devices. 

2.x Specification
PCI Express Architecture Link Layer Test Specification Revision 2.0

This test specification primarily covers testing of all PCI Express Port types for compliance with the link layer requirements in Chapter 3 of the PCI Express Base Specification. At this point, this specification does not describe the full set of PCI Express tests for all link layer requirements. Going forward, as the testing gets mature, it is expected that more tests may be added as deemed necessary.

2.x Specification
PCI Code and Assignment Specification Revision 1.3

This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications.

1.x Specification
PCI Code and Assignment Specification Revision 1.3 with Change Bar

This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications.

1.x Specification
PCI Express External Cabling Specification Revision 2.0

This is a companion specification to the PCI Express Base Specification. Its primary focus is the implementation of cabled PCI Express®. The discussions are confined to copper cabling and their connector requirements to meet the PCI Express signaling needs at 5.0 GT/s. No assumptions are made regarding the implementation of PCI Express compliant Subsystems on either side of the cabled Link; e.g., PCI Express Card Electromechanical (CEM), ExpressCard5 ™, ExpressModule™, PXI Express™, system board, or any other form factor. Such form factors are covered in other separate specifications.

2.x Specification
PCI Express External Cabling Specification Revision 2.0 with Change Bar

This is a companion specification to the PCI Express Base Specification. Its primary focus is the implementation of cabled PCI Express®. The discussions are confined to copper cabling and their connector requirements to meet the PCI Express signaling needs at 5.0 GT/s. No assumptions are made regarding the implementation of PCI Express compliant Subsystems on either side of the cabled Link; e.g., PCI Express Card Electromechanical (CEM), ExpressCard5 ™, ExpressModule™, PXI Express™, system board, or any other form factor. Such form factors are covered in other separate specifications.

2.x Specification
Combined Antenna Tuning/Coexistence Signal ECR

Modify the PCI Express Mini Card specification to define a new interface for tunable antennas. Modify the PCI Express Mini Card specification to enable existing coexistence signals to operate simultaneously with new tuneable antenna control signals.

2.x ECN
PCI Express Mini Card Electromechanical Specification Revision 2.0 with Change Bar

This specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 2.0. Where this specification does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs.

2.x Specification
PCI Express Mini Card Electromechanical Specification Revision 2.0

This specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 2.0. Where this specification does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs.

2.x Specification
PCI Code and Assignment Specification Revision 1.2

This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications.

1.x Specification
PCI Code and Assignment Specification Revision 1.2 with Change Bar

This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications.

1.x Specification
PCI Code and Assignment Specification Revision 1.1

This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications.

1.x Specification
PCI Code and Assignment Specification Revision 1.1 with Change Bar

This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications.

1.x Specification
Downstream Port Containment (DPC)

This ECN defines a new error containment mechanism for Downstream Ports as well as minor enhancements that improve asynchronous card removal. Downstream Port Containment (DPC) is the automatic disabling of the Link below a Downstream Port following an uncorrectable error. This prevents the potential spread of data corruption (all TLPs subsequent to the error are prevented from propagating either Upstream or Downstream) and enables error recovery if supported by software.

3.x ECN
Lightweight Notification (LN) Protocol

This optional normative ECN defines a simple protocol where a device can register interest in one or more cachelines in host memory, and later be notified via a hardware mechanism when any registered cachelines are updated.

3.x ECN
8.0 GT/s Receiver Impedance

Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the following LTSSM states: Polling, Rx_L0s, L1, L2, and Disabled.

3.x ECN
PASID Translation

The Process Address Space ID (PASID) ECN to the Base PCI Express Specification defines the PASID TLP Prefix. This companion ECN is optional normative and defines PASID TLP Prefix usage rules for ATS and PRI.

1.x ECN
Process Address Space ID (PASID)

This optional normative ECN defines an End-End TLP Prefix for conveying additional attributes associated with a request. The PASID TLP Prefix is an End-End TLP Prefix as defined in the PCI Express Base Specification. Routing elements that support End-End TLP Prefixes (i.e. have the End-End TLP Prefix Supported bit Set in the Device Capabilities 2 register) can correctly forward TLPs containing a PASID TLP Prefix.

1.x ECN
Errata for the PCI Express Base Specification Revision 2.1 2.x Errata
PCI Express Base Specification Revision 3.0 with Change Bar

This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.

3.x Specification
PCI Express Base Specification Revision 3.0

This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.

3.x Specification
REF CLK Delayed from CLKREQ# Assertion

This ECR requests making a change to the CLKREQ# asserted low to clock active timing when latency tolerance reporting is supported and enabled for the function. The change would be to allow this specified value to exceed 400ns up to a limit consistent with the latency value established by the Latency Tolerance Reporting (LTR) mechanism.

1.x ECN
Protocol Multiplexing

This involves a minor upward compatible change in Chapter 3, Chapter 4 and a new Appendix T.

3.x ECN
End-End TLP Prefix Changes for RCs

 This change allows for all Root Ports with the End-End TLP Prefix Supported bit Set to have different values for the Max End-End TLP Prefixes field in the Device Capabilities 2 register. It also changes and clarifies error handling for a Root Port receiving a TLP with more End-End TLP Prefixes than it supports.

3.x ECN
Second Wireless Disable Pin

This ECN is for the functional addition of a second wireless disable signal (W_DISABLE2#) as a new definition of Pin 51 (Reserved). When this optional second wireless disable signal is not implemented by the system, the original intent of a single wireless disable signal disabling all radios on the add-in card when asserted is still required.

1.x ECN
Single Root I/O Virtualization and Sharing Specification Revision 1.1 with Change Bar

The purpose of this document is to specify PCI™ I/O virtualization and sharing technology. The specification is focused on single root topologies; e.g., a single computer that supports virtualization technology.

1.x Specification
Single Root I/O Virtualization and Sharing Specification Revision 1.1

The purpose of this document is to specify PCI™ I/O virtualization and sharing technology. The specification is focused on single root topologies; e.g., a single computer that supports virtualization technology.

1.x Specification
CEM Support Power

 ECR covers proposed modification of Section 4.2 Power Consumption within the CEM Specification version 2.0.

2.x ECN
ASPM Optionality

Prior to this ECN, all PCIe external Links were required to support ASPM L0s. This ECN changes the Base Specification to permit ASPM L0s support to be optional unless the applicable formfactor specification explicitly requires it.

2.x ECN
Optimized Buffer Flush/Fill

This ECR proposes to add a new mechanism for platform central resource (RC) power state information to be communicated to Devices. This mechanism enables Optimized Buffer Flush/Fill (OBFF) by allowing the platform to indicate optimal windows for device bus mastering & interrupt activity. Devices can use internal buffering to shape traffic to fit into these optimal windows, reducing platform power impact.

2.x ECN
PCI Express Base Specification Revision 2.1 with Change Bar

This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.

2.x Specification
Errata for the PCI Express Base Specification Revision 2.0 2.x Errata
Address Translation Services Revision 1.1

This specification describes the extensions required to allow PCI Express Devices to interact with an address translation agent (TA) in or above a Root Complex (RC) to enable translations of DMA addresses to be cached in the Device. The purpose of having an Address Translation Cache (ATC) in a Device is to minimize latency and to provide a scalable distributed caching solution that will improve I/O performance while alleviating TA resource pressure. This specification must be used in conjunction with the PCI Express Base Specification, Revision 1.1, and associated ECNs.

1.x Specification
TLP Prefix

Emerging usage model trends indicate a requirement for increase in header size fields to provide additional information than what can be accommodated in currently defined TLP header sizes. The TLP Prefix mechanism extends the header size by adding DWORDS to the front of headers that carry additional information.

2.x ECN
System Board Eye Height Specification Update

This ECN modifies the system board transmitter path requirements (VTXS and VTXS_d) at 5 GT/s. As a consequence the minimum requirements for the add-in card receiver path sensitivity at 5 GT/s are also updated.

2.x ECN
TLP Processing Hints

This optional normative ECR defines a mechanism by which a Requester can provide hints on a per transaction basis to facilitate optimized processing of transactions that target Memory Space. The architected mechanisms may be used to enable association of system processing resources (e.g. caches) with the processing of Requests from specific Functions or enable optimized system specific (e.g. system interconnect and Memory) processing of Requests.

2.x ECN
Extended Tag Enable Default

The change allows a Function to use Extended Tag fields (256 unique tag values) by default; this is done by allowing the Extended Tag Enable control field to be set by default.

2.x ECN
PCI Express Architecture Configuration Space Test Specification Revision 2.0

This document primarily covers PCI Express testing of root complexes, switches, bridges, and endpoints for the standard configuration mechanisms, registers, and features in Chapter 7 of the PCI Express Base Specification, Revision 2.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.

2.x Specification
Latency Tolerance Reporting

This ECR proposes to add a new mechanism for Endpoints to report their service latency requirements for Memory Reads and Writes to the Root Complex such that central platform resources (such as main memory, RC internal interconnects, snoop resources, and other resources associated with the RC) can be power managed without impacting Endpoint functionality and performance.

2.x ECN
PCI Express Architecture Transaction Layer Test Specification Revision 2.0

This document contains a list of Test Assertions and a set of Test Definitions pertaining to the Transaction Layer. Assertions are statements of spec requirements which are measured by the algorithm details as specified in the Test Definitions. “Basic Functional Tests” are Test Algorithms which perform basic tests for key elements of Transaction Layer device functionality. This document does not describe a full set of PCI Express tests and assertions and is in no way intended to measure products for full design validation. Tests described here should be viewed as tools to checkpoint the result of product validation – not as a replacement for that effort.

2.x Specification
ID-Based Ordering

This ECN proposes to add a new ordering attribute which devices may optionally support to provide enhanced performance for certain types of workloads and traffic patterns. The new ordering attribute relaxes ordering requirements between unrelated traffic by comparing the Requester/Completer IDs of the associated TLPs.

2.x ECN
Dynamic Power Allocation

DPA (Dynamic Power Allocation) extends existing PCIe device power management to provide active (D0) device power management substates for appropriate devices, while comprehending existing PCIe PM Capabilities including PCI-PM and Power Budgeting.

2.x ECN
Multi-Root I/O Virtualization and Sharing Specification Revision 1.0

The purpose of this document is to specify PCI® I/O virtualization and sharing technology. The specification is focused on multi-root topologies; e.g., a server blade enclosure that uses a PCI Express® Switch-based topology to connect server blades to PCI Express Devices or PCI Express to-PCI Bridges and enable the leaf Devices to be serially or simultaneously shared by one or more System Images (SI). Unlike the Single Root IOV environment, independent SI may execute on disparate processing components such as independent server blades.

1.x Specification
Multicast

This optional normative ECN adds Multicast functionality to PCI Express by means of an Extended Capability structure for applicable Functions in Root Complexes, Switches, and components with Endpoints. The Capability structure defines how Multicast TLPs are identified and routed. It also provides means for checking and enforcing send permission with Function-level granularity. The ECN identifies Multicast errors and adds an MC Blocked TLP error to AER for reporting those errors.

2.x ECN
Internal Error Reporting

PCI Express (PCIe) defines error signaling and logging mechanisms for errors that occur on a PCIe interface and for errors that occur on behalf of transactions initiated on PCIe. It does not define error signaling and logging mechanisms for errors that occur within a component or are unrelated to a particular PCIe transaction.

2.x ECN
Resizable BAR Capability

This optional ECN adds a capability for Functions with BARs to report various options for sizes of their memory mapped resources that will operate properly. Also added is an ability for software to program the size to configure the BAR to.

2.x ECN
Atomic Operations

This optional normative ECN defines 3 new PCIe transactions, each of which carries out a specific Atomic Operation (“AtomicOp”) on a target location in Memory Space. The 3 AtomicOps are FetchAdd (Fetch and Add), Swap (Unconditional Swap), and CAS (Compare and Swap). FetchAdd and Swap support operand sizes of 32 and 64 bits. CAS supports operand sizes of 32, 64, and 128 bits.

2.x ECN
PCI Express® 225 W/300 W High Power Card Electromechanical Specification Revision 1.0

The main objective of this specification is to support PCI Express® add-in cards that require higher power than specified in the PCI Express Card Electromechanical Specification and the PCI Express x16 Graphics 150W-ATX Specification.

1.x Specification
Address Translation Services 1.0 Specification Errata 1.x Errata
PCI Express Mini Card Electromechanical Specification Revision 1.2

This specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 1.1. Where this specification does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs.

1.x Specification
PCI Express Mini Card Electromechanical Specification Revision 1.2 with Change Bar

This specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 1.1. Where this specification does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs.

1.x Specification
Single Root I/O Virtualization and Sharing Specification Revision 1.0

The purpose of this document is to specify PCI™ I/O virtualization and sharing technology. The specification is focused on single root topologies; e.g., a single computer that supports virtualization technology.

1.x Specification
Alternative Routing-ID Interpretation (ARI)

For virtualized and non-virtualized environments, a number of PCI-SIG member companies have requested that the current constraints on number of Functions allowed per multi-Function Device be increased to accommodate the needs of next generation I/O implementations. This ECR specifies a new method to interpret the Device Number and Function Number fields within Routing IDs, Requester IDs, and Completer IDs, thereby increasing the number of Functions that can be supported by a single Device.

2.x ECN
PCI Express Card Electromechanical Specification Revision 2.0 with Change Bar

This specification is a companion for the PCI Express Base Specification, Revision 2.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express® Mini Card are covered in other separate specifications.

2.x Specification
PCI Express Card Electromechanical Specification Revision 2.0

This specification is a companion for the PCI Express Base Specification, Revision 2.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express® Mini Card are covered in other separate specifications.

2.x Specification
Address Translation Services Revision 1.0

This specification describes the extensions required to allow PCI Express Devices to interact with an address translation agent (TA) in or above a Root Complex (RC) to enable translations of DMA addresses to be cached in the Device. The purpose of having an Address Translation Cache (ATC) in a Device is to minimize latency and to provide a scalable distributed caching solution that will improve I/O performance while alleviating TA resource pressure. This specification must be used in conjunction with the PCI Express Base Specification, Revision 1.1, and associated ECNs.

1.x Specification
Errata for the PCI Express Base Specification Revision 1.1 1.x Errata
PCI Express External Cabling Specification Revision 1.0

This is a companion specification to the PCI Express Base Specification. Its primary focus is the implementation of cabled PCI Express®. The discussions are confined to copper cabling and their connector requirements to meet the PCI Express signaling needs at 2.5 GT/s. No assumptions are made regarding the implementation of PCI Express compliant Subsystems on either side of the cabled Link; e.g., PCI Express Card Electromechanical (CEM), ExpressCard™, ExpressModule™, PXI Express™, system board, or any other form factor. Such form factors are covered in other separate specifications.

1.x Specification
PCI Express Base Specification Revision 2.0

This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.

2.x Specification
PCI Express Card Electromechanical Specification Revision 1.1

This specification is a companion for the PCI Express Base Specification, Revision 1.1. Its primary focus is the implementation of an evolutionary strategy with the current PCI desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express Mini Card are covered in other separate specifications.

1.x Specification
PCI Express Card Electromechanical Specification Revision 1.1 with Change Bar

This specification is a companion for the PCI Express Base Specification, Revision 1.1. Its primary focus is the implementation of an evolutionary strategy with the current PCI desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express Mini Card are covered in other separate specifications.

1.x Specification
PCI Express Base Specification Revision 1.1

This specification describes the PCI Express architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express specification.

1.x Specification
PCI Express Base Specification Revision 1.1 with Change Bar

This specification describes the PCI Express architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express specification.

1.x Specification
PCI Express ExpressModule Electromechanical Specification Revision 1.0

This document is a companion specification to the PCI Express Base Specification. Its primary focus is the implementation of a modular I/O form factor that is focused on the needs of workstations and servers from mechanicals and electrical requirements. The discussions are confined to the modules and their chassis slots requirements. Other form factors are covered in other separate specifications.

1.x Specification
PCI Express x16 Graphics 150W-ATX Specification Revision 1.0

The objectives of this specification are Support for PCI Express™ graphics add-in cards that are higher power than specified in the PCI Express Card Electromechanical Specification, Forward looking for future scalability, Allow evolution of the PC architecture including graphics, Upgradeability, and Enhanced end user experience.

1.x Specification
PCI Express Architecture Mobile Graphics Low-Power Addendum to the PCI Express Base Specification Revision 1.0

This addendum to the PCI Express Base 1.0a describes a low power extension intended primarily to support the reduced power requirements of mobile platforms. Its scope is restricted to the electrical layer and corresponds to Section 4.3 of PCI Express Base 1.0a.

1.x Specification
PCI Express to PCI/PCI-X Bridge Specification Revision 1.0

This specification describes the PCI Express to PCI/PCI-X bridge (also referred to herein as PCI Express bridge) architecture, interface requirements, and the programming model.

1.x Specification
Technology: PCI Conventional
Specification Title Spec Rev Document Type Release Date
PCI Firmware Specification Revision 3.2

This document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.

3.x Specification
Enhanced Allocation (EA) for Memory and I/O Resources

Enhanced Allocation is an optional Conventional PCI Capability that may be implemented by Functions to indicate fixed (non reprogrammable) I/O and memory ranges assigned to the Function, as well as supporting new resource “type” definitions and future extensibility to also support reprogrammable allocations.

3.x ECN
ACPI Additions for FW Latency Optimizations

This ECR provides two additional ACPI DSM functions to inform OS about the possible time reduction opportunities:

3.x ECN
PCIe Hot Plug

This ECN affects the PCI Firmware Specification v3.1 and allows certain errors to be suppressed by platform if software stack ensured error containment. Also removes the implementation note in section 4.5.2.4 which is not representative of OS behavior.

3.x ECN
UEFI Related Updates

Update the references to the latest UEFI Specification. Make clarifications in 5.1.2 that the pointers to the Device List, the Configuration Utility Code header and the DMTF CLP Entry Point are not applicable to the UEFI Option ROMs.

3.x ECN
Changing Class Code for InfiniBand Adapter

This ECN updates the subclass ID description in the Class Code & Capability ID Specification.

3.x ECN
PCI Firmware Specification Revision 3.1

This document describes the hardware independent firmware interface for managing PCI™, PCI-X, and PCI Express® systems in a host computer.

3.x Specification
Class Code & Capability ID Extraction

This ECN extracts the Class Code definitions from Appendix D and the Capability ID definitions from Appendix H, for consolidation into a new standalone document that’s easier to maintain. The new document will also consolidate Extended Capability definitions from the PCIe Base spec and various other PCIe specs.

3.x ECN
PCIe Device Labeling under Operating Systems

This ECR proposes a mechanism (new extension to _DSM) to make the device names/labels under Operating Systems deterministic. Currently, there is no well defined mechanism to consistently associate platform specific device names and instances of a device type under operating system. As a result, instance labels for specific device types under various operating systems (ex: ethx label for networking device instance under Linux OS) do not always map into the platform designated device labels. Additionally, the instance labels can change based on the system configuration. For example, under Linux operating systems, the “eth0” label does not necessarily map to the first embedded networking device as designed in a given platform. Depending on the hardware bus topology, current configuration including the number and type of networking adapters installed, the eth0 label assignment could change in a given platform.

3.x ECN
ACPI Additions for ASPM, OBFF, LTR ECNs

A number of PCIe base specifications ECNs have been approved that require software support. In some cases, platform firmware needs to know if the OS running supports certain features, or the OS needs to be able to request control of certain features from platform firmware. In other cases, the OS needs to know information about the platform that cannot be discovered through PCI enumeration, and ACPI must be used to supply the additional information.

3.x ECN
Update DMTF SM CLP Specification References

This update references to sections in the DMTF Server Management Command Line Protocol (SM CLP) Specification (DSP0214) to match the most recent version SM CLP Specification (v1.0.2). It also clarifies that the references to the DMTF SM CLP specification are referencing v1.0.2. and adds a reference to the DMTF SM CLP specification in section 1.2 Reference Documents.

3.x ECN
UEFI PCI Services Update

This is a request to update the UEFI PCI Services. No functional changes. In the case of the UGA reference, UGA has been obsolete by the UEFI Specification and is replaced by the new GOP.

3.x ECN
Unoccupied Slot Power Hand-off State Clarification

This ECN allows the unoccupied slots' power to be off at hand-off, which is a reasonable implementation and many systems implement that way today.

3.x ECN
PCI Option ROM CLP

This ECN rectifies the differences between the DMTF SM CLP Specification and its supporting documents with the current PCI Firmware 3.0 Specification. Also, it clarifies the supporting documents required for successfully implementing CLP in an X86 PCI FW 3.0 compatible option ROM.

3.x ECN
Errata for PCI 3.0 3.x Errata
Advanced Capabilities for Conventional PCI

For conventional PCI devices integrated into a PCI Express Root Complex, this defines an optional capability structure that includes selected advanced features originally defined for PCI Express. This capability is intended to be extensible in the future. For the initial definition, the Transactions Pending (TP) and Function Level Reset (FLR) are included.

3.x ECN
PCI_OSC Clarifications

This ECN attempts to make clarifications such that the system firmware and multiple operating systems can have the same interpretation of the specification and work interoperably.

3.x ECN
Ignore PCI Boot Configuration_DSM Function

This ECN adds a function to the _DSM Definitions for PCI to provide an indication to an operating system that it can ignore the PCI boot configuration setup by the firmware during system initialization.

3.x ECN
PCI Firmware Specification Revision 3.0

This document describes the hardware independent firmware interface for managing PCI, PCI-X, and PCI Express™ systems in a host computer.

3.x Specification
Interrupt Line Register Usage

This ECN is a request for modifications to the paragraphs describing the Interrupt Line Register usage for the PCI-to-PCI-Bridge. The purpose is to clarify the differences between the usages on PC-compatible systems and DIG64-compliant systems.

1.x ECN
Generic Capability Structure for SATA Host Bus Adapters

The functional changes proposed involve the definition of a new Capabilities List ID (and associated Capability register set). This new Capabilities ID will identify to system firmware (BIOS/OROM), a Serial ATA (SATA) host bus adapter’s (HBA) support of optional features that may be defined in the particular SATA HBA specification (i.e. Advanced Host Controller Interface - AHCI).

3.x ECN
PCI Bus Power Management Interface Specification Revision 1.2

The goal of this specification is to establish a standard set of PCI peripheral power management hardware interfaces and behavioral policies. Once established, this infrastructure enables an operating system to intelligently manage the power of PCI functions and buses.

1.x Specification
PCI Local Bus Specification Revision 3.0

This document contains the formal specifications of the protocol, electrical, and mechanical features of the PCI Local Bus Specification, Revision 3.0, as the production version effective February 3, 2004. The PCI Local Bus Specification, Revision 2.3, issued March 29, 2002, is not superseded by this specification.

3.x Specification
PCI Local Bus Specification Revision 3.0 with Change Bar

This document contains the formal specifications of the protocol, electrical, and mechanical features of the PCI Local Bus Specification, Revision 3.0, as the production version effective February 3, 2004. The PCI Local Bus Specification, Revision 2.3, issued March 29, 2002, is not superseded by this specification.

3.x Specification
Errata for PCI 2.3 2.x Errata
SATA Class Code ECN

Create a new class code for SerialATA host-based adapters (HBAs) that can be identified by system software. The new class code will allow for system software to identify a controller as being attached to serial ATA devices and serial attached SCSI devices. This will help system software load drivers that may be specific to these interfaces.

3.x ECN
MSI-X

Extend the current MSI functionality to support a larger number of MSI vectors, plus a separate and independent Message Address and Message Data for each MSI vector. Allow more flexibility when SW allocates fewer MSI vectors than requested by HW. Enable per-vector masking capability.

2.x ECN
MSI-X

Extend the current MSI functionality to support a larger number of MSI vectors, plus a separate and independent Message Address and Message Data for each MSI vector. Allow more flexibility when SW allocates fewer MSI vectors than requested by HW. Enable per-vector masking capability.

3.x ECN
PCI-to-PCI Bridge Architecture Specification Revision 1.2

This specification defines the behavior of a compliant PCI-to-PCI bridge. A PCI-to-PCI bridge that conforms to this specification and the PCI Local Bus Specification is a compliant implementation. Compliant bridges may differ from each other in performance and, to some extent, functionality.

1.x Specification
PCI-to-PCI Bridge Architecture Specification Revision 1.2 with Change Bar

This specification defines the behavior of a compliant PCI-to-PCI bridge. A PCI-to-PCI bridge that conforms to this specification and the PCI Local Bus Specification is a compliant implementation. Compliant bridges may differ from each other in performance and, to some extent, functionality.

1.x Specification
SHPC Memory Access Granularity

Restrict PCI Standard Hot-Plug (SHPC) device drivers to a memory access granularity of maximum one DWORD (aligned) when reading or writing to the SHPC memory space.

1.x ECN
SHPC Extensions for PCI-X 2.0

Changes are to the PCI Standard Hot-Plug Controller and Subsystem Specification, Revision 1.0. This ECN extends the Standard Hot-plug Controller Specification to support the additional PCI-X speeds and modes allowed by the PCI-X 2.0 specification. Specifically, this ECN provides the required hardware and software extensions needed to support the new PCI-X 2.0 speeds of 266 and 533 and also the software extensions needed to control PCI-X 2.0 mode ECC and parity operation.

1.x ECN
PCI/PCI-X Connector Contact Finish Changes

The intent of this ECR is to update the PCI base specifications to include PCI connector metallurgical practices which have been commonly accepted or introduced since the original wording was drafted before the PCI 2.0 specification. With an overwhelming majority of PCI and PCI-X connectors shipped in the world that do not meet the PCI specification for contact finish plating, the most efficient way to rectify the situation is to correct the specification.

2.x ECN
PCI/PCI-X Connector Contact Finish Changes

The intent of this ECR is to update the PCI base specifications to include PCI connector metallurgical practices which have been commonly accepted or introduced since the original wording was drafted before the PCI 2.0 specification. With an overwhelming majority of PCI and PCI-X connectors shipped in the world that do not meet the PCI specification for contact finish plating, the most efficient way to rectify the situation is to correct the specification.

3.x ECN
PCI Local Bus Specification Revision 2.3

This document contains the formal specifications of the protocol, electrical, and mechanical features of the PCI Local Bus Specification, Revision 2.3, as the production version effective March 29, 2002. The PCI Local Bus Specification, Revision 2.2, issued December 18, 1998, is superseded by this specification.

2.x Specification
PCI Hot-Plug Specification Revision 1.1

The primary objective of this specification is to enable higher availability of file and application servers by standardizing key aspects of the process of removing and installing PCI add-in cards while the system is running. Although these same principles can be applied to desktop and portable systems using PCI buses, the operations described here target server platforms.

1.x Specification
PCI Standard Hot-Plug Controller and Subsystem Specification Revision 1.0

The primary purpose of this document is to specify a standard implementation of a PCI Hot-Plug Controller called the Standard Hot-Plug Controller (SHPC).

1.x Specification
Mini PCI Specification Revision 1.0

The Mini PCI Specification defines an alternate implementation for small form factor PCI cards referred to in this specification as a Mini PCI Card. This specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Local Bus Specification.

1.x Specification
PCI Bios Specification Revision 2.1

This document describes the software interface presented by the PCI BIOS functions. This interface provides a hardware independent method of managing PCI devices in a host computer.

2.x Specification