PCI-SIG Developers Conference 2019 Agenda

The sessions below are categorized by track subject according to the following key:

(1) PCI Express
(2) PCI-SIG Architecture
(3) Members Implementation
(4) Members Implementation

Day One - Tuesday, June 18, 2019
Time Title
8:00 am - 9:00 am
9:00 am - 9:30 am
Registration in Foyer
Introductory Keynote / Annual Members Meeting
9:30 am - 10:30 am (1) PCIe 5.0 Electrical Update    
(2) PCI-SIG Architecture Overview 
(3) Accurate Determination of Chip Package Insertion Loss  
(4) Accurate End-to-End PCIe 5.0 System Modeling

10:30 am - 11:30 am

(1) PCIe CEM 5.0 Previews
(2) PCIe Cable Update   
(3) PCI Express Link Training and Protocol Debug Techniques 
(4) Impact of Bit Errors in PCIe 5.0 for Latency-critical Applications
11:30 am - 1:00 pm Lunch and Exhibit
1:00 pm - 2:00 pm (1) PCIe 5.0 PHY Logical
(2) PCI Express Basics    
(3) Enable PCIe 5.0 System Design with Ethernet Architectures
(4) Correlating Methods and Demystifying 32GT/s Receiver Testing
2:00 pm - 3:00 pm (1) PCIe 4.0 Compliance: Electrical Deep Dive  
(2) PCIe Electrical Basics
(3) Refclk Measurement Best Practices for 16GT/s and 32GT/s Systems
(4) Sensor Fusion and Data-in-Motion Processing for Autonomous Vehicles
3:00 pm - 3:30 pm PM Break and Exhibit
3:30 pm - 4:30 pm (1) PCIe 5.0 Protocol Update    
(2) PCI Express M.2 Updates  
(3) Reliability and Serviceability Features in a PCIe Controller
(4) Comparing PCIe Solutions for Emulation and Simulation
4:30 pm - 5:30 pm PCIe Panel Discussion
5:30 pm - 7:00 pm PCI-SIG Evening Reception
Day Two - Wednesday, June 19, 2018
Time Title
 9:00 am - 10:00 am (1) PCIe 5.0 Electrical Update
(2) PCI Express Basics
(3) PCB Bandwidth Analysis for PCIe at 16GT/s and 32GT/s
(4) Design and Analysis of a 32GT/s SerDes for PCIe 5.0 in 10nm
10:00 am - 10:30 am AM Break and Exhibit
10:30 am - 11:30 am (1) PCIe CEM 5.0 Previews
(2) PCIe Cable Update
(3) PCIe Architectures for Chip-to-Chip Interconnects
(4) Refclk Testing for PCI Express Base Specification 5.0
11:30 am - 12:30 pm (1) PCIe 5.0 PHY Logical
(2) PCIe Platform Component Security Enhancements
(3) Adaptable SmartNIC Where Hot Plug Meets Bare-Metal Cloud
(4) 32GT/s Test Platform for AI and ML Implementations
12:30 pm - 1:30 pm Lunch and Exhibit
1:30 pm - 2:30 pm (1) PCIe 4.0 Compliance: Protocol Deep Dive
(2) PCIe Electrical Basics
(3) Signal Integrity Challenges & Solutions for PCIe 5.0 System Topologies 
(4) When Debugging on Hardware is your Last Solution
2:30 pm - 3:30 pm (1) PCIe 5.0 Protocol Update
(2) PCI Express M.2 Updates
(3) Analysis of Different Types of PCIe Receiver Calibration Channels
(4) PCIe 5.0 Precoding Requirements and Verification Challenges