PCI-SIG specifications define standards driving the industry-wide compatibility of peripheral component interconnects. Members regularly review them, providing commentary and change requests when necessary. These requests are considered by technical workgroups and applied as appropriate, resulting in collaboratively devised specifications benefiting millions of platforms and add-in devices.
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PCI Code & ID Assignment Specifications
The PCI Code & ID Assignment Specifications are accessible to non-members without charge here. PCI-SIG members can download these specifications directly from the Specifications Library below.
The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in
both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution.
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This proposal introduces a new version of the M.2 co...view moreThis proposal introduces a new version of the M.2 connector with improved amperage per pin to 1 A, card outline changes with increased component area options.
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For the SFF-8639 module (U.2) specification, this EC...view moreFor the SFF-8639 module (U.2) specification, this ECR increases +3.3 VAux current. The category of SMBus inactive current is eliminated and replaced with a default current of 8 mA. Additionally, the 5 mA active current requirement is eliminated and replaced with a 25 mA requirement if MCTP or I3C Basic traffic is initiated by the platform when Vaux power is enabled while 12V is disabled.
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This ECR increases the specified leakage and capacit...view moreThis ECR increases the specified leakage and capacitance tolerances for Auxiliary I/O signals.
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The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution.
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The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution.
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This ECN adds 1.8V IO support to Type 1216, Type 222...view moreThis ECN adds 1.8V IO support to Type 1216, Type 2226, and Type 3026 LGAs. This support adds two previously defined pins to these LGAs: • VIO_CFG, a 1.8V IO support indication (one pin) • VIO 1.8V, a 1.8V IO Voltage source (one pin) The VIO 1.8 V signal is intended as an IO supply and reference voltage for host interface sideband signals PERST#, CLKREQ#, and PEWAKE# and additional signals such as SUSCLK, W_DISABLE1#, W_DISABLE2#. This provides IO voltage flexibility to enable IO voltage levels other than 3.3V in the applicable M.2 form factors. The VIO_CFG signal is intended to provide the Platform an indication of the IO voltage capabilities of the M.2 Adapter installed. In cases where the Platform detects that an incompatible Adapter is installed, the Platform may choose to not power the Adapter or isolate the affected sideband signals to avoid damage or interface instability.
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This test specification is intended to confirm if a ...view moreThis test specification is intended to confirm if a stand-alone Retimer is compliant to the PCI Base Specification.
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Summary of the Functional Changes...view moreSummary of the Functional Changes
I. Add core voltages 0.75 V in PWR_3 rail for BGA SSD.
II. Add new pin configuration including 0.75 V pin.
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This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0.
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This ECR establishes two operational modes for use o...view moreThis ECR establishes two operational modes for use of the Power Disable (PWRDIS) signal. The existing mode allowed use of the signal for coordinated shutdown of the PCIe device, but was optimized for a power-on reset of a non-responsive device. The new mode reduces PWRDIS minimum asserted hold time from 5 s to 100 ms for use in a coordinated shutdown with an emphasis on entry and exit times from D3cold.
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Add 3052 and 3060 form factors for WWAN modules usin...view moreAdd 3052 and 3060 form factors for WWAN modules using Socket 2 with Key B and Key C.
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The focus of this specification is on PCI Express® (...view moreThe focus of this specification is on PCI Express® (PCIe®) solutions utilizing the SFF-8639 connector interface. Form factors include, but are not limited to, those described in the SFF-8201 Form Factor Drive Dimensions Specification. Other form factors, such as PCI Express Card Electromechanical are documented in other independent specifications.
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Proposes repurposing five RFU pins in the Type 1113 ...view moreProposes repurposing five RFU pins in the Type 1113 (11.5mm x 13mm) BGA ball map to be optionally used for indicating PWR1, PWR2, and PWR3 supply voltage requirements to the platform. If this ECR is implemented then all 5 pins need to be implemented. Adds a 1.0 V power supply option for PWR3 for both BGA1113 and BGA1620.
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The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution.
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The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution.
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This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices
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This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices
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This is a companion specification to the PCI Express...view moreThis is a companion specification to the PCI Express Base Specification. The primary focus of this specification is the implementation of cabled PCI Express®. No assumptions are made regarding the implementation of PCI Express-compliant Subsystems on either side of the cabled Link (PCI Express Card Electromechanical (CEM), ExpressCard™, ExpressModule™, PXI Express™, or any other form factor). Such form factors are covered in separate specifications
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Smaller lithography has led to smaller pad sizes whi...view moreSmaller lithography has led to smaller pad sizes which has increased parasitics on inputs. For the Card Electromechanical Specification, this ECR increases Cin, the maximum input pin capacitance on 3.3 V logic signals (applies to PERST# and PWRBRK#) from 7 pF to 20 pF (see CEM Table 3).
For the M.2 specification, this ECR increases M.2 CIN, the maximum input pin capacitance for both 3.3 V logic signal (applies to PERST#, see M.2 Table 4-1) and 1.8 V logic signals (applies to PERST# and PEWAKE# (when used for OBFF signaling), see M.2 Table 4-2) from 10 pF to 20 pF. This capacitance increase is large enough for known upcoming lithographies.
It had not been clear what the measurement point was for CIN in CEM or M.2 specifications. This 18 ECN extends the COUT measurement point specified in M.2 to apply to CIN and COUT for both 19 CEM and M.2 specifications.
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This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.
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This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.
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High Volume Manufacturing (HVM) and other manufactur...view moreHigh Volume Manufacturing (HVM) and other manufacturer test processes benefit from the ability to set Add-in Card (AIC) modes that enable multiplexing of standard connector pins for test specific use. This ECR defines a method to allow the system to enable a Manufacturer Test Mode (MFG) on the AIC through the standard interface connector prior to shipping the AIC. This ECR to the CEM specification is consistent with Manufacturing Mode ECN to the SFF-8639 specification.
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This specification is a companion for the PCI Expres...view moreThis specification is a companion for the PCI Express® Base Specification, Revision 4.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications.
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This specification is a companion for the PCI Expres...view moreThis specification is a companion for the PCI Express® Base Specification, Revision 4.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications.
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This test specification primarily covers testing of ...view moreThis test specification primarily covers testing of PCI Express® Device and Port types for compliance with the link layer and transaction layer requirements of the PCI Express Base Specification. Device and Port types that do not have a link (e.g., Root Complex Integrated Endpoints, Root 10 Complex Event Collectors) are not tested under this test specification. While the test environment can accommodate the presence of a Retimer, it will not test the Retimer itself. At this point, this test specification does not describe the full set of PCI Express tests for all link layer or transaction layer requirements.
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This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.
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This document primarily covers PCI Express testing o...view moreThis document primarily covers PCI Express testing of all defined PCI Express device types and RCRBs for the standard Configuration Space mechanisms, registers, and features in Chapter 6 of the PCI Local Bus Specification (Base 3.x or earlier only) and Chapters 7, 9 (Base 4.x or later only), 10 (Base 4.x or later only) of the PCI Express Base Specification (some additional tested registers are described in other specifications that are referenced in the individual test description). This specification does not describe the full set of PCI Express tests for these devices.
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This ECN defines four new services under ACS for Dow...view moreThis ECN defines four new services under ACS for Downstream Ports, primarily to address issues when ACS redirect mechanisms are used to ensure that DMA Requests from Functions under the direct control of VMs are always routed correctly to the Translation Agent in the host. Three of the services provide redirect or blocking of Upstream Memory Requests that target areas not covered by other ACS services. The fourth service enables the blocking of Upstream I/O Requests, addressing a concern with VM-controlled Functions maliciously sending I/O Requests.
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This ECN effects the PCI Express Base Specification,...view moreThis ECN effects the PCI Express Base Specification, Version 4.0. ePTM is an improvement on the existing Precision Time Measurement capability that provides improved detection and handling of error cases. ePTM quickly identifies and resolves errors that may cause clocks to become desynchronized.
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This ECN updates several areas related to hot-plug f...view moreThis ECN updates several areas related to hot-plug functionality, mostly related to Async hot-plug, which is now growing in importance due to its widespread use with NVMe SSDs. All new functionality is optional. This ECN affects the PCIe 4.0 Base Specification.
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This ECN enhances Root Complex Event Collectors (RCE...view moreThis ECN enhances Root Complex Event Collectors (RCECs) to allow them to be associated with Devices located on additional Bus numbers.
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This ECN allows Address Translation Requests and Com...view moreThis ECN allows Address Translation Requests and Completions to support the Relaxed Ordering bit, where are currently defined to be Reserved for these types of TLPs. The proposal preserves interoperability with older Translation Agents.
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Link Activation allows software to temporarily disab...view moreLink Activation allows software to temporarily disable Link power management, enabling the avoidance of the architecturally mandated stall for software-initiated L1 Substate exits.
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This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
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This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
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Provide an optional mechanism to indicate to softwar...view moreProvide an optional mechanism to indicate to software the results of a hardware validation of Expansion ROM contents.
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