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PCI Code & ID Assignment Specifications
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The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in
both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution.
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This test specification is intended to confirm if a ...view moreThis test specification is intended to confirm if a stand-alone Retimer is compliant to the PCIe Base Specification. This test specification is not intended to test Retimers based only on the Extension Devices ECN to the PCI Express Base Specification, Revision 3.x. This test specification only covers stand-alone Retimers in common clock mode, and is not intended to test Retimers integrated onto a platform or an add-in card.
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The focus of this specification is on PCI Express® (...view moreThe focus of this specification is on PCI Express® (PCIe®) solutions utilizing the SFF-8639 (also known as U.2) connector interface. Form factors include, but are not limited to, those described in the SFF-8201 Form Factor Drive Dimensions Specification. Other form factors, such as PCI Express Card Electromechanical are documented in other independent specifications.
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This ECR introduces updated dimensioning and toleran...view moreThis ECR introduces updated dimensioning and tolerances for the 48VHPWR header and plug. The 48VHPWR connector has been removed from the specification. The name for the new connector is 48V1x2. Ordering of the sense pins is changed so that Sense0 and Sense1 pins are located farthest from each other. This reordering is incompatible with the pre-existing connector definition. Per workgroup input, there are no known implementations of the 48VHPWR header and plug as of this publication date. References to external specifications are added.
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This proposal introduces a new version of the M.2 co...view moreThis proposal introduces a new version of the M.2 connector with improved amperage per pin to 1 A, card outline changes with increased component area options.
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For the SFF-8639 module (U.2) specification, this EC...view moreFor the SFF-8639 module (U.2) specification, this ECR increases +3.3 VAux current. The category of SMBus inactive current is eliminated and replaced with a default current of 8 mA. Additionally, the 5 mA active current requirement is eliminated and replaced with a 25 mA requirement if MCTP or I3C Basic traffic is initiated by the platform when Vaux power is enabled while 12V is disabled.
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This Card Electromechanical (CEM) specification is a...view moreThis Card Electromechanical (CEM) specification is a companion for the PCI Express® Base Specification, Revision 5.0. Its primary focus is the implementation of an evolutionary strategy with earlier PCI™ desktop/server mechanical and electrical specifications.
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This Card Electromechanical (CEM) specification is a...view moreThis Card Electromechanical (CEM) specification is a companion for the PCI Express® Base Specification, Revision 5.0. Its primary focus is the implementation of an evolutionary strategy with earlier PCI™ desktop/server mechanical and electrical specifications.
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Informational testing on test case 54-20 will give D...view moreInformational testing on test case 54-20 will give DUT vendor information about their implementation of the capability. Not passing judgement on test case 54-20 will prevent DUTs from incorrect failing the DUT or false passing the DUT at Compliance Workshops.
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The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution.
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This ECR removes the transmitter jitter test require...view moreThis ECR removes the transmitter jitter test requirement for 32 GT/s systems. Transmitter jitter test remains a requirement for 32 GT/s Add-in Cards.
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This ECN replaces existing drawings for the 12VHPWR ...view moreThis ECN replaces existing drawings for the 12VHPWR cable plug with 2 different options.
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Expands power excursion to 12V power rail in PCIE CE...view moreExpands power excursion to 12V power rail in PCIE CEM connector in addition to 12VHPWR and 48VHPWR connectors but excludes legacy 2x3 and 2x4 auxiliary power connectors from power excursion specification.
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The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution.
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The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution.
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This ECR increases the specified leakage and capacit...view moreThis ECR increases the specified leakage and capacitance tolerances for Auxiliary I/O signals.
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This ECN adds 1.8V IO support to Type 1216, Type 222...view moreThis ECN adds 1.8V IO support to Type 1216, Type 2226, and Type 3026 LGAs. This support adds two previously defined pins to these LGAs: • VIO_CFG, a 1.8V IO support indication (one pin) • VIO 1.8V, a 1.8V IO Voltage source (one pin) The VIO 1.8 V signal is intended as an IO supply and reference voltage for host interface sideband signals PERST#, CLKREQ#, and PEWAKE# and additional signals such as SUSCLK, W_DISABLE1#, W_DISABLE2#. This provides IO voltage flexibility to enable IO voltage levels other than 3.3V in the applicable M.2 form factors. The VIO_CFG signal is intended to provide the Platform an indication of the IO voltage capabilities of the M.2 Adapter installed. In cases where the Platform detects that an incompatible Adapter is installed, the Platform may choose to not power the Adapter or isolate the affected sideband signals to avoid damage or interface instability.
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This document defines the TEE Device Interface Secur...view moreThis document defines the TEE Device Interface Security Protocol (TDISP) - An architecture for trusted I/O virtualization providing the following functions: 1. Establishing a trust relationship between a TVM and a device. 2. Securing the interconnect between the host and device. 3. Attach and detach a TDI to a TVM in a trusted manner.
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This test specification is intended to confirm if a ...view moreThis test specification is intended to confirm if a stand-alone Retimer is compliant to the PCI Base Specification.
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Summary of the Functional Changes...view moreSummary of the Functional Changes
I. Add core voltages 0.75 V in PWR_3 rail for BGA SSD.
II. Add new pin configuration including 0.75 V pin.
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Summary of the Functional Changes...view moreSummary of the Functional Changes
Changing the RFU pin in the 12VHPWR connector sideband to Sense1. Adding 150W and 300W power capabilities to the encoding options for Sense0 and Sense1. Makes Card_CBL_PRES required to be tied to ground with 4.7 kΩ resistor.
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Transmitter jitter requirements at 32 GT/s are being...view moreTransmitter jitter requirements at 32 GT/s are being added for system board and Add-in Card.
Affected Document: PCI Express Card Electromechanical Specification Revision 5.0, Version 1.0
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This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 5.0.
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This document primarily covers PCI Express testing o...view moreThis document primarily covers PCI Express testing of all defined Device Types and RCRBs for the standard Configuration Space mechanisms, registers, and features.
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This test specification primarily covers testing of ...view moreThis test specification primarily covers testing of PCI Express® Device and Port types for compliance with the link layer and transaction layer requirements of the PCI Express Base Specification.
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This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0.
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Original IDE ECN plus IDE items included in final Ba...view moreOriginal IDE ECN plus IDE items included in final Base 5.0 Errata. Changebar version relative to original IDE ECN also available.
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This is a change bar version of the Integrity and Da...view moreThis is a change bar version of the Integrity and Data Encryption (IDE) ECN – Revision A.
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This ECR establishes two operational modes for use o...view moreThis ECR establishes two operational modes for use of the Power Disable (PWRDIS) signal. The existing mode allowed use of the signal for coordinated shutdown of the PCIe device, but was optimized for a power-on reset of a non-responsive device. The new mode reduces PWRDIS minimum asserted hold time from 5 s to 100 ms for use in a coordinated shutdown with an emphasis on entry and exit times from D3cold.
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This change allows for cards to exceed maximum power...view moreThis change allows for cards to exceed maximum power levels currently defined in the CEM spec to enable higher performance for certain workloads. This change clearly defines limits for these excursions to allow system designers to properly design power subsystems to enable these excursions.
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The long-standing requirement for a component’s LTSS...view moreThe long-standing requirement for a component’s LTSSM to enter Detect state within 20 ms of the end of Fundamental Reset is relaxed (extended) to 100 ms for components that support >5 GT/s Link speeds.
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Add 3052 and 3060 form factors for WWAN modules usin...view moreAdd 3052 and 3060 form factors for WWAN modules using Socket 2 with Key B and Key C.
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Describes a method to measure Tx jitter parameters a...view moreDescribes a method to measure Tx jitter parameters at 32 GT/s accurately by using a Jitter Measurement Pattern. This replaces the S-parameter de-embedding method. In this method, a CTLE-based equalization instead of S-parameter based de-embedding gain filter is applied to the captured Tx waveform to mitigate signal degradation due to frequency-dependent channel loss. The CTLE-based equalization is defined by the 32 GT/s reference CTLE curves. The proposed method with the use of clock pattern in the lane under test and compliance pattern in other lanes avoids the inaccuracy of the S-parameter based de-embedding that results from the amplification of the real-time oscilloscope floor noise by the de-embedding gain filter. The Tx jitter measurement methods for 8.0 and 16.0 GT/s have been kept unchanged.
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Introduces a fitting-based Tx preset measurement met...view moreIntroduces a fitting-based Tx preset measurement methodology that extracts Tx equalization coefficients from measured step responses with and without Tx equalization. Consequently, it overcomes a few limitations of the current DC voltage-level based methodology where the ratio of DC voltage levels of various presets is used to avoid measurement complexity due to high frequency-dependent loss. Since the use of the ratio of DC voltage levels do not guarantee the correct use of Tx equalization coefficients and constant voltage swing across presets, the existing DC voltage-level based measurement methodology may give incorrect results if the Tx equalization coefficients and voltage swing significantly deviate from the intended values for the specified Tx presets.
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This Card Electromechanical (CEM) specification is a...view moreThis Card Electromechanical (CEM) specification is a companion for the PCI Express® Base Specification, Revision 5.0. Its primary focus is the implementation of an evolutionary strategy with earlier PCI™ desktop/server mechanical and electrical specifications.
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This Card Electromechanical (CEM) specification is a...view moreThis Card Electromechanical (CEM) specification is a companion for the PCI Express® Base Specification, Revision 5.0. Its primary focus is the implementation of an evolutionary strategy with earlier PCI™ desktop/server mechanical and electrical specifications.
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The focus of this specification is on PCI Express® (...view moreThe focus of this specification is on PCI Express® (PCIe®) solutions utilizing the SFF-8639 connector interface. Form factors include, but are not limited to, those described in the SFF-8201 Form Factor Drive Dimensions Specification. Other form factors, such as PCI Express Card Electromechanical are documented in other independent specifications.
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Proposes repurposing five RFU pins in the Type 1113 ...view moreProposes repurposing five RFU pins in the Type 1113 (11.5mm x 13mm) BGA ball map to be optionally used for indicating PWR1, PWR2, and PWR3 supply voltage requirements to the platform. If this ECR is implemented then all 5 pins need to be implemented. Adds a 1.0 V power supply option for PWR3 for both BGA1113 and BGA1620.
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Integrity & Data Encryption (IDE) provides confi...view moreIntegrity & Data Encryption (IDE) provides confidentiality, integrity, and replay protection for TLPs. It flexibly supports a variety of use models, while providing broad interoperability. The cryptographic mechanisms are aligned to current industry best practices and can be extended as security requirements evolve. The security model considers threats from physical attacks on Links, including cases where an adversary uses lab equipment, purpose-built interposers, malicious Extension Devices, etc. to examine data intended to be confidential, modify TLP contents, & reorder and/or delete TLPs. TLP traffic can be secured as it transits Switches, extending the security model to address threats from reprogramming Switch routing mechanisms or using “malicious” Switches. Compared to the Member Review copy, and consistent with the “NOTICE TO REVIEWERS” in that copy, this final revision contains significant revisions to the key management protocol in order to align it closely with the DMTF’s Secured Messages using SPDM Specification, which was not available at the time the Member Review copy was prepared. Additionally, the final copy includes significant improvements in protection against Adversary-in-the-Middle attacks, and, consistent with member feedback received in response to the query regarding key size for AES-GCM applied to IDE TLPs, supports only the 256b key size.
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The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution.
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The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and higher integration of functions onto a single form factor module solution.
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This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices
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This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices
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Loosens restrictions on use of PASID to allow PASID ...view moreLoosens restrictions on use of PASID to allow PASID to be applied to Memory Requests using Translated addresses (AT=Translated).
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Smaller lithography has led to smaller pad sizes whi...view moreSmaller lithography has led to smaller pad sizes which has increased parasitics on inputs. For the Card Electromechanical Specification, this ECR increases Cin, the maximum input pin capacitance on 3.3 V logic signals (applies to PERST# and PWRBRK#) from 7 pF to 20 pF (see CEM Table 3).
For the M.2 specification, this ECR increases M.2 CIN, the maximum input pin capacitance for both 3.3 V logic signal (applies to PERST#, see M.2 Table 4-1) and 1.8 V logic signals (applies to PERST# and PEWAKE# (when used for OBFF signaling), see M.2 Table 4-2) from 10 pF to 20 pF. This capacitance increase is large enough for known upcoming lithographies.
It had not been clear what the measurement point was for CIN in CEM or M.2 specifications. This 18 ECN extends the COUT measurement point specified in M.2 to apply to CIN and COUT for both 19 CEM and M.2 specifications.
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This is a companion specification to the PCI Express...view moreThis is a companion specification to the PCI Express Base Specification. The primary focus of this specification is the implementation of cabled PCI Express®. No assumptions are made regarding the implementation of PCI Express-compliant Subsystems on either side of the cabled Link (PCI Express Card Electromechanical (CEM), ExpressCard™, ExpressModule™, PXI Express™, or any other form factor). Such form factors are covered in separate specifications
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This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.
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This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.
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This ECN defines a new Request, the Deferrable Memor...view moreThis ECN defines a new Request, the Deferrable Memory Write (DMWr), that requires the Completer to return an acknowledgement to the Requester, and provides a mechanism for the recipient to defer (temporarily refuse to service) the Request.
To provide space for the required control registers, this ECN also defines an Extended Capability, the Device 3 Extended Capability, to provide Device Capabilities 3, Device Control 3, and Device Status 3 registers. This Extended Capability is required for DMWr support, but can also be applied to other uses besides DMWr, and therefore can be implemented by Functions that do not support DMWr.
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This ECR defines an adaptation of the data objects a...view moreThis ECR defines an adaptation of the data objects and underlying protocol defined in the DMTF SPDM specification (https://www.dmtf.org/dsp/DSP0274) for PCIe components, providing a mechanism to verify the component configuration and firmware/executables (Measurement) and hardware identities (Authentication). “Firmware” in this context includes configuration settings in addition to executable code. This protocol can be operated via the Data Object Exchange (DOE) mechanism, or through other means, for example via MCTP messaging conveyed using PCIe Messages, or via SMBus, I2C, or other management I/O. Data Object Exchange (DOE) is defined in the Data Object Exchange ECN to the PCIe Base Specification Rev 4.0, 5.0, approved on 12 Mar 2020.
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This ECR defines an optional Extended Capability str...view moreThis ECR defines an optional Extended Capability structure and associated control mechanisms to provide System Firmware/Software the ability to perform data object exchanges with a Function or RCRB.
To support Component Measurement and Authentication (CMA) accessible in-band via host firmware/software, Data Object Exchange (DOE) is required, and CMA motivates the need for DOE, although broader uses are anticipated.
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Revision A (January 30, 2020) corrects an error in t...view moreRevision A (January 30, 2020) corrects an error in the original revision (September 29, 2019). The ATS Memory Attributes Supported field in the ATS Capabilities Register is now assigned bit location 8. It was previously assigned bit location 7. The affected text is highlighted in Table 10-9: ATS Capability Register.
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Shadow Functions are permitted to be assigned only w...view moreShadow Functions are permitted to be assigned only where currently unused Functions reside. The Function declaring the shadowing is permitted to overflow its Transaction ID space over into the Shadow Function. The impetus for defining Shadow Functions is to provide more Transaction ID space without increasing the Tag field, since there are no straightforward means to do that at the current time.
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Due to ambiguity in earlier versions of the PCIe Bas...view moreDue to ambiguity in earlier versions of the PCIe Base Specification two different interpretations of the byte positions in the PTM ResponseD Message Propagation Delay field have been implemented. This ECR defines mechanisms that new hardware can implement to support the adaptation to either of the interpretations.
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High Volume Manufacturing (HVM) and other manufactur...view moreHigh Volume Manufacturing (HVM) and other manufacturer test processes benefit from the ability to set Add-in Card (AIC) modes that enable multiplexing of standard connector pins for test specific use. This ECR defines a method to allow the system to enable a Manufacturer Test Mode (MFG) on the AIC through the standard interface connector prior to shipping the AIC. This ECR to the CEM specification is consistent with Manufacturing Mode ECN to the SFF-8639 specification.
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This specification is a companion for the PCI Expres...view moreThis specification is a companion for the PCI Express® Base Specification, Revision 4.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications.
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This specification is a companion for the PCI Expres...view moreThis specification is a companion for the PCI Express® Base Specification, Revision 4.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications.
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This document primarily covers PCI Express testing o...view moreThis document primarily covers PCI Express testing of all defined PCI Express device types and RCRBs for the standard Configuration Space mechanisms, registers, and features in Chapter 6 of the PCI Local Bus Specification (Base 3.x or earlier only) and Chapters 7, 9 (Base 4.x or later only), 10 (Base 4.x or later only) of the PCI Express Base Specification (some additional tested registers are described in other specifications that are referenced in the individual test description). This specification does not describe the full set of PCI Express tests for these devices.
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This test specification primarily covers testing of ...view moreThis test specification primarily covers testing of PCI Express® Device and Port types for compliance with the link layer and transaction layer requirements of the PCI Express Base Specification. Device and Port types that do not have a link (e.g., Root Complex Integrated Endpoints, Root 10 Complex Event Collectors) are not tested under this test specification. While the test environment can accommodate the presence of a Retimer, it will not test the Retimer itself. At this point, this test specification does not describe the full set of PCI Express tests for all link layer or transaction layer requirements.
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This document provides test descriptions for PCI Exp...view moreThis document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.
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There are four informative ...view moreThere are four informative "changebar" versions of the PCI Express Base 5.0 Specification comparing Base 5.0/1.0 to Base 5.0/0.9 and comparing Base 4.0 and Base 5.0. HTML and PDF versions are provided. Both versions are derived from common source material but have different characteristics, and readers may wish to reference both. These documents are non-normative - the NCB PCI Express Base Specification Revision 5.0, Version 1.0 (NCB-PCI_Express_Base_5.0r1.0-2019-05-22.pdf) is the normative version of this specification.
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This specification describes the PCI Express archite...view moreThis specification describes the PCI Express architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
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This ECN defines four new services under ACS for Dow...view moreThis ECN defines four new services under ACS for Downstream Ports, primarily to address issues when ACS redirect mechanisms are used to ensure that DMA Requests from Functions under the direct control of VMs are always routed correctly to the Translation Agent in the host. Three of the services provide redirect or blocking of Upstream Memory Requests that target areas not covered by other ACS services. The fourth service enables the blocking of Upstream I/O Requests, addressing a concern with VM-controlled Functions maliciously sending I/O Requests.
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This ECN effects the PCI Express Base Specification,...view moreThis ECN effects the PCI Express Base Specification, Version 4.0. ePTM is an improvement on the existing Precision Time Measurement capability that provides improved detection and handling of error cases. ePTM quickly identifies and resolves errors that may cause clocks to become desynchronized.
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This ECN updates several areas related to hot-plug f...view moreThis ECN updates several areas related to hot-plug functionality, mostly related to Async hot-plug, which is now growing in importance due to its widespread use with NVMe SSDs. All new functionality is optional. This ECN affects the PCIe 4.0 Base Specification.
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This ECN enhances Root Complex Event Collectors (RCE...view moreThis ECN enhances Root Complex Event Collectors (RCECs) to allow them to be associated with Devices located on additional Bus numbers.
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This ECN allows Address Translation Requests and Com...view moreThis ECN allows Address Translation Requests and Completions to support the Relaxed Ordering bit, where are currently defined to be Reserved for these types of TLPs. The proposal preserves interoperability with older Translation Agents.
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Link Activation allows software to temporarily disab...view moreLink Activation allows software to temporarily disable Link power management, enabling the avoidance of the architecturally mandated stall for software-initiated L1 Substate exits.
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This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
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This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.
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Provide an optional mechanism to indicate to softwar...view moreProvide an optional mechanism to indicate to software the results of a hardware validation of Expansion ROM contents.
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