Specifications

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Specifications Library

Technology: PCI Express
Specification Title Spec Rev Document Type Release Date
Cin Maximum Increase ECN
Smaller lithography has led to smaller pad sizes whi...view more Smaller lithography has led to smaller pad sizes which has increased parasitics on inputs. For the Card Electromechanical Specification, this ECR increases Cin, the maximum input pin capacitance on 3.3 V logic signals (applies to PERST# and PWRBRK#) from 7 pF to 20 pF (see CEM Table 3). For the M.2 specification, this ECR increases M.2 CIN, the maximum input pin capacitance for both 3.3 V logic signal (applies to PERST#, see M.2 Table 4-1) and 1.8 V logic signals (applies to PERST# and PEWAKE# (when used for OBFF signaling), see M.2 Table 4-2) from 10 pF to 20 pF. This capacitance increase is large enough for known upcoming lithographies. It had not been clear what the measurement point was for CIN in CEM or M.2 specifications. This 18 ECN extends the COUT measurement point specified in M.2 to apply to CIN and COUT for both 19 CEM and M.2 specifications. show less
4.x ECN
PCI Express External Cabling Specification Revision 3.0a (Change Bar)
This is a companion specification to the PCI Express...view more This is a companion specification to the PCI Express Base Specification. The primary focus of this specification is the implementation of cabled PCI Express®. No assumptions are made regarding the implementation of PCI Express-compliant Subsystems on either side of the cabled Link (PCI Express Card Electromechanical (CEM), ExpressCard™, ExpressModule™, PXI Express™, or any other form factor). Such form factors are covered in separate specifications show less
4.x Specification
PCI Express Architecture PHY Test Specification Revision 4.0, Version 1.01 (Change Bar)
This document provides test descriptions for PCI Exp...view more This document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices. show less
4.x Specification
PCI Express Architecture PHY Test Specification Revision 4.0, Version 1.01 (Clean)
This document provides test descriptions for PCI Exp...view more This document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices. show less
4.x Specification
Component Measurement and Authentication (CMA) ECN
This ECR defines an adaptation of the data objects a...view more This ECR defines an adaptation of the data objects and underlying protocol defined in the DMTF SPDM specification (https://www.dmtf.org/dsp/DSP0274) for PCIe components, providing a mechanism to verify the component configuration and firmware/executables (Measurement) and hardware identities (Authentication). “Firmware” in this context includes configuration settings in addition to executable code. This protocol can be operated via the Data Object Exchange (DOE) mechanism, or through other means, for example via MCTP messaging conveyed using PCIe Messages, or via SMBus, I2C, or other management I/O. Data Object Exchange (DOE) is defined in the Data Object Exchange ECN to the PCIe Base Specification Rev 4.0, 5.0, approved on 12 Mar 2020. show less
5.x ECN
Deferrable Memory Write (DMWr) and Device 3 Extended Capability ECN
This ECN defines a new Request, the Deferrable Memor...view more This ECN defines a new Request, the Deferrable Memory Write (DMWr), that requires the Completer to return an acknowledgement to the Requester, and provides a mechanism for the recipient to defer (temporarily refuse to service) the Request. To provide space for the required control registers, this ECN also defines an Extended Capability, the Device 3 Extended Capability, to provide Device Capabilities 3, Device Control 3, and Device Status 3 registers. This Extended Capability is required for DMWr support, but can also be applied to other uses besides DMWr, and therefore can be implemented by Functions that do not support DMWr. show less
5.x ECN
Data Object Exchange (DOE) ECN
This ECR defines an optional Extended Capability str...view more This ECR defines an optional Extended Capability structure and associated control mechanisms to provide System Firmware/Software the ability to perform data object exchanges with a Function or RCRB. To support Component Measurement and Authentication (CMA) accessible in-band via host firmware/software, Data Object Exchange (DOE) is required, and CMA motivates the need for DOE, although broader uses are anticipated. show less
5.x ECN
ATS Memory Attributes ECN, Revision A
Revision A (January 30, 2020) corrects an error in t...view more Revision A (January 30, 2020) corrects an error in the original revision (September 29, 2019). The ATS Memory Attributes Supported field in the ATS Capabilities Register is now assigned bit location 8. It was previously assigned bit location 7. The affected text is highlighted in Table 10-9: ATS Capability Register. show less
5.x ECN
Shadow Functions ECN
Shadow Functions are permitted to be assigned only w...view more Shadow Functions are permitted to be assigned only where currently unused Functions reside. The Function declaring the shadowing is permitted to overflow its Transaction ID space over into the Shadow Function. The impetus for defining Shadow Functions is to provide more Transaction ID space without increasing the Tag field, since there are no straightforward means to do that at the current time. show less
5.x ECN
PTM Byte Adaptation ECN
Due to ambiguity in earlier versions of the PCIe Bas...view more Due to ambiguity in earlier versions of the PCIe Base Specification two different interpretations of the byte positions in the PTM ResponseD Message Propagation Delay field have been implemented. This ECR defines mechanisms that new hardware can implement to support the adaptation to either of the interpretations. show less
5.x ECN
Errata for the PCI Express Base Specification Revision 5.0 5.x Errata
Manufacturer Test Mode Pin ECN
High Volume Manufacturing (HVM) and other manufactur...view more High Volume Manufacturing (HVM) and other manufacturer test processes benefit from the ability to set Add-in Card (AIC) modes that enable multiplexing of standard connector pins for test specific use. This ECR defines a method to allow the system to enable a Manufacturer Test Mode (MFG) on the AIC through the standard interface connector prior to shipping the AIC. This ECR to the CEM specification is consistent with Manufacturing Mode ECN to the SFF-8639 specification. show less
4.x ECN
PCI Express Card Electromechanical Specification Revision 4.0, Version 1.0 (Clean)
This specification is a companion for the PCI Expres...view more This specification is a companion for the PCI Express® Base Specification, Revision 4.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications. show less
4.x Specification
PCI Express Card Electromechanical Specification Revision 4.0, Version 1.0 (Change Bar)
This specification is a companion for the PCI Expres...view more This specification is a companion for the PCI Express® Base Specification, Revision 4.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications. show less
4.x Specification
Errata for the PCI Express Base Specification Revision 4.0
Final Release against Base Revision 4.0 ...view more Final Release against Base Revision 4.0 show less
4.x Errata
PCI Express Architecture Link Layer and Transaction Layer Test Specification Revision 4.0, Version 1.0
This test specification primarily covers testing of ...view more This test specification primarily covers testing of PCI Express® Device and Port types for compliance with the link layer and transaction layer requirements of the PCI Express Base Specification. Device and Port types that do not have a link (e.g., Root Complex Integrated Endpoints, Root 10 Complex Event Collectors) are not tested under this test specification. While the test environment can accommodate the presence of a Retimer, it will not test the Retimer itself. At this point, this test specification does not describe the full set of PCI Express tests for all link layer or transaction layer requirements. show less
4.x Specification
PCI Express Architecture PHY Test Specification Revision 4.0, Version 1.0
This document provides test descriptions for PCI Exp...view more This document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building Add-in Cards or system boards to the PCI Express Card Electromechanical Specification 4.0. This specification does not describe the full set of PCI Express tests and assertions for these devices. show less
4.x Specification
PCI Express Architecture Configuration Space Test Specification Revision 4.0, Version 1.0
This document primarily covers PCI Express testing o...view more This document primarily covers PCI Express testing of all defined PCI Express device types and RCRBs for the standard Configuration Space mechanisms, registers, and features in Chapter 6 of the PCI Local Bus Specification (Base 3.x or earlier only) and Chapters 7, 9 (Base 4.x or later only), 10 (Base 4.x or later only) of the PCI Express Base Specification (some additional tested registers are described in other specifications that are referenced in the individual test description). This specification does not describe the full set of PCI Express tests for these devices. show less
4.x Specification
PCI Express Base Specification Revision 5.0, Version 1.0 (Change Bar Versions)
There are four informative ...view more There are four informative "changebar" versions of the PCI Express Base 5.0 Specification comparing Base 5.0/1.0 to Base 5.0/0.9 and comparing Base 4.0 and Base 5.0. HTML and PDF versions are provided. Both versions are derived from common source material but have different characteristics, and readers may wish to reference both. These documents are non-normative - the NCB PCI Express Base Specification Revision 5.0, Version 1.0 (NCB-PCI_Express_Base_5.0r1.0-2019-05-22.pdf) is the normative version of this specification. show less
5.x Specification
PCI Express Base Specification Revision 5.0, Version 1.0
This specification describes the PCI Express archite...view more This specification describes the PCI Express architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. show less
5.x Specification
ACS Enhanced Capabilities ECN
This ECN defines four new services under ACS for Dow...view more This ECN defines four new services under ACS for Downstream Ports, primarily to address issues when ACS redirect mechanisms are used to ensure that DMA Requests from Functions under the direct control of VMs are always routed correctly to the Translation Agent in the host. Three of the services provide redirect or blocking of Upstream Memory Requests that target areas not covered by other ACS services. The fourth service enables the blocking of Upstream I/O Requests, addressing a concern with VM-controlled Functions maliciously sending I/O Requests. show less
4.x ECN
Enhanced PCIe Precision Time Measurement (ePTM) ECN
This ECN effects the PCI Express Base Specification,...view more This ECN effects the PCI Express Base Specification, Version 4.0. ePTM is an improvement on the existing Precision Time Measurement capability that provides improved detection and handling of error cases. ePTM quickly identifies and resolves errors that may cause clocks to become desynchronized. show less
4.x ECN
Async Hot-Plug Updates ECN
This ECN updates several areas related to hot-plug f...view more This ECN updates several areas related to hot-plug functionality, mostly related to Async hot-plug, which is now growing in importance due to its widespread use with NVMe SSDs. All new functionality is optional. This ECN affects the PCIe 4.0 Base Specification. show less
4.x ECN
Errata for the PCI Express® Base Specification Revision 4.0 4.x Errata
Root Complex Event Collector Bus Number Association ECN
This ECN enhances Root Complex Event Collectors (RCE...view more This ECN enhances Root Complex Event Collectors (RCECs) to allow them to be associated with Devices located on additional Bus numbers. show less
4.x ECN
Address Translation Relaxed Ordering ECN
This ECN allows Address Translation Requests and Com...view more This ECN allows Address Translation Requests and Completions to support the Relaxed Ordering bit, where are currently defined to be Reserved for these types of TLPs. The proposal preserves interoperability with older Translation Agents. show less
4.x ECN
PCIe Link Activation ECN
Link Activation allows software to temporarily disab...view more Link Activation allows software to temporarily disable Link power management, enabling the avoidance of the architecturally mandated stall for software-initiated L1 Substate exits. show less
4.x ECN
PCI Express® Base Specification Revision 4.0, Version 1.0
This specification describes the PCI Express® archit...view more This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. show less
4.x Specification
PCI Express® Base Specification Revision 4.0, Version 1.0 (Change Bar)
This specification describes the PCI Express® archit...view more This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. show less
4.x Specification
Expansion ROM Validation ECN
Provide an optional mechanism to indicate to softwar...view more Provide an optional mechanism to indicate to software the results of a hardware validation of Expansion ROM contents. show less
4.x ECN