Webinars

Upcoming Webinars:

    Past Webinars:

    Integrity and Data Encryption (IDE) ECN Deep Dive

    August 25, 2020
    9:00 – 10:00AM PT

    View the Webinar Slides

    Developers must focus on a wide number of considerations when securing the wide spectrum of systems, devices and components. Not only must they protect key assets against a litany of attacks, but they must also prioritize securing the entire component lifecycle. Over the past few years, PCI-SIG® has focused on optimizing security features within the PCI Express® library of specifications. This webinar will focus on the key aspects of the latest emerging security ECN: Integrity and Data Encryption (IDE).

    Attendees learned about the next level details of motivations and use models, including Link vs. Selective, how security is managed, required elements outside of PCIe® technology including software, system construction and industry infrastructure. The webinar also provided an overview of Device’s responsibilities in maintaining security, such as how keys must be secured, paths around encryption eliminated/blocked and how to handle debug. Finally, the webinar outlined specific areas for feedback such as key size and key programming protocol.

    Participants:

    • David Harriman, PCI-SIG Protocol Work Group Chair, Intel

    August 5, 2020
    8:00 – 9:15AM CST / 9:00AM – 10:15AM EST

    PCI Express® (PCIe®) architecture has provided the I/O connectivity for computing, communication, and storage platforms satisfying the power-efficient and low-latency requirements of cloud, enterprise, PC, embedded, IoT, automotive, and mobile market segments for two decades. However, the demand for additional performance in power constrained devices and data-hungry server, client, embedded, cloud and edge segments keeps increasing. To continue to meet the performance needs of these segments, PCI-SIG® continues its nearly three decade history of successfully delivering performance doubling with the development of the upcoming PCIe 6.0 specification.

    Attendees will learn more about what is driving the quick transition to PCIe 6.0, including an updated specification release timeline. The webinar will feature a deep dive into the PCIe 6.0 architecture metrics. It introduces the approach PCIe 6.0 specification is taking to offer new features like PAM4 encoding and FEC, while preserving its low-latency characteristics required for a Load-Store interconnect and full backwards compatibility.

    In this webinar replay at a new APAC-friendly time, members will be able to participate in a live Q&A with the presenter.

    Participants:

    • Dr. Debendra Das Sharma, PCI-SIG Board member and an Intel Fellow and Director of I/O Technology and Standards Group
    June 4, 2020
    8:00 – 9:00AM PT
     

    View the Webinar Slides

    PCI Express® (PCIe®) architecture has provided the I/O connectivity for computing, communication, and storage platforms satisfying the power-efficient and low-latency requirements of cloud, enterprise, PC, embedded, IoT, automotive, and mobile market segments for two decades. However, the demand for additional performance in power constrained devices and data-hungry server, client, embedded, cloud and edge segments keeps increasing. To continue to meet the performance needs of these segments, PCI-SIG® continues its nearly three decade history of successfully delivering performance doubling with the development of the upcoming PCIe 6.0 specification.

    In this webinar, attendees learned more about what is driving the quick transition to PCIe 6.0, including an updated specification release timeline. The webinar will feature a deep dive into the PCIe 6.0 architecture metrics. It introduced the approach PCIe 6.0 specification is taking to offer new features like PAM-4 encoding and FEC, while preserving its low-latency characteristics required for a Load-Store interconnect and full backwards compatibility.

    Participants:

    • Dr. Debendra Das Sharma, PCI-SIG Board member and an Intel Fellow and Director of I/O Technology and Standards Group

    Emerging Form Factors: EDSFF Overview
    April 8, 2020
    8:00 – 9:00AM PT

    View the Recorded Webinar

    View the Webinar Slides

    Enterprise & Data Center SSD Form Factor (EDSFF) is one of the newest form factors to emerge in recent years. Its goal is to develop a stronger data center system-optimized design than traditional SSD form factors like M.2 or U.2. EDSFF has shown that it’s able to meet customer need for storage devices with its high density, capacity and performance.

    This webinar will include an overview of the relationship between EDSFF and the PCI Express® (PCIe®) specifications and discuss various use cases for E1.L, E1.S and E3. Finally, they will outline the step-by-step process of how you can build a drive utilizing EDSFF form factors.

    Participants:

    • Tom Friend, President and CEO at Illuminosi
    • Jonmichael Hands, Sr. Strategic Planner, Product Manager at Intel
    • Jonathan Hinkle, Executive Director and Distinguished Researcher - Systems Architecture at Lenovo

    Retimers to the Rescue: PCI Express® Specifications Reach Their Full Potential
    October 9, 2019
    8:00 – 9:00AM

    View the Recorded Webinar

    View the Webinar Slides

    As PCI Express® specifications continue to double the transfer rates of previous generations, the technology can address a variety of needs for data-demanding applications. However, along with the progression of PCIe® specifications, challenges like signal integrity and channel insertion loss arise as well. Retimers are mixed signal analog/digital devices that are protocol-aware and have the ability to fully recover data, extract the embedded clock and retransmit a fresh copy of the data using a clean clock. These devices are fully defined in the PCI Express base specification and are used to combat issues that PCI Express technology faces.

    In this PCI-SIG® hosted webinar, Kurt Lender of Intel and Casey Morrison of Astera Labs will offer solutions to conquer signal integrity and channel insertion loss challenges, explain the diagnostic capabilities of retimer technology and more.

    Participants:

    • Kurt Lender is the Senior Ecosystem Enabling Manager for Intel Corporation and a Marketing Workgroup Chair at PCI-SIG
    • Casey Morrison is the head of Systems and Applications at Astera Labs and a PCI-SIG member