8:00 – 9:00AM PT
PCI Express® (PCIe®) architecture has provided the I/O connectivity for computing, communication, and storage platforms satisfying the power-efficient and low-latency requirements of cloud, enterprise, PC, embedded, IoT, automotive, and mobile market segments for two decades. However, the demand for additional performance in power constrained devices and data-hungry server, client, embedded, cloud and edge segments keeps increasing. To continue to meet the performance needs of these segments, PCI-SIG® continues its nearly three decade history of successfully delivering performance doubling with the development of the upcoming PCIe 6.0 specification.
In this webinar, attendees learned more about what is driving the quick transition to PCIe 6.0, including an updated specification release timeline. The webinar will feature a deep dive into the PCIe 6.0 architecture metrics. It introduced the approach PCIe 6.0 specification is taking to offer new features like PAM-4 encoding and FEC, while preserving its low-latency characteristics required for a Load-Store interconnect and full backwards compatibility.
- Dr. Debendra Das Sharma, PCI-SIG Board member and an Intel Fellow and Director of I/O Technology and Standards Group
Emerging Form Factors: EDSFF Overview
April 8, 2020
8:00 – 9:00AM PT
Enterprise & Data Center SSD Form Factor (EDSFF) is one of the newest form factors to emerge in recent years. Its goal is to develop a stronger data center system-optimized design than traditional SSD form factors like M.2 or U.2. EDSFF has shown that it’s able to meet customer need for storage devices with its high density, capacity and performance.
This webinar will include an overview of the relationship between EDSFF and the PCI Express® (PCIe®) specifications and discuss various use cases for E1.L, E1.S and E3. Finally, they will outline the step-by-step process of how you can build a drive utilizing EDSFF form factors.
- Tom Friend, President and CEO at Illuminosi
- Jonmichael Hands, Sr. Strategic Planner, Product Manager at Intel
- Jonathan Hinkle, Executive Director and Distinguished Researcher - Systems Architecture at Lenovo
Retimers to the Rescue: PCI Express® Specifications Reach Their Full Potential
October 9, 2019
8:00 – 9:00AM
As PCI Express® specifications continue to double the transfer rates of previous generations, the technology can address a variety of needs for data-demanding applications. However, along with the progression of PCIe® specifications, challenges like signal integrity and channel insertion loss arise as well. Retimers are mixed signal analog/digital devices that are protocol-aware and have the ability to fully recover data, extract the embedded clock and retransmit a fresh copy of the data using a clean clock. These devices are fully defined in the PCI Express base specification and are used to combat issues that PCI Express technology faces.
In this PCI-SIG® hosted webinar, Kurt Lender of Intel and Casey Morrison of Astera Labs will offer solutions to conquer signal integrity and channel insertion loss challenges, explain the diagnostic capabilities of retimer technology and more.
- Kurt Lender is the Senior Ecosystem Enabling Manager for Intel Corporation and a Marketing Workgroup Chair at PCI-SIG
- Casey Morrison is the head of Systems and Applications at Astera Labs and a PCI-SIG member