PCI-SIG Developers Conference Israel 2022 Agenda

Tel Aviv, Israel 

Day One - Monday, October 24, 2022 

Time                                               Title 
8:00 am – 9:00 am Registration & Breakfast
9:00 am  – 10:30 am  PCI Express Basics & Background (Richard Solomon) 
10:30 am – 11:00 am AM Break & Exhibit
11:00 am – 12:00 pm PCIe 6.0 Electrical Update (Mohiuddin Mazumder)
12:00 pm – 1:00 pm Lunch & Exhibit
1:00 pm – 2:00 pm PCIe CEM Updates (Manisha Nilange) 
2:00 pm – 3:00 pm  PCIe 6.0 Protocol Update (Joe Cowan)
3:00 pm – 3:30 pm PM Break & Exhibit
3:30 pm – 4:30 pm PCIe 6.0 PHY Logical (Joe Cowan) 
4:30 pm – 5:30 pm  PCIe Compliance Updates (Manisha Nilange)

 

Day Two - Tuesday, October 25, 2022    

Time                                               Title 
8:00 am – 8:30 am                      Breakfast & Exhibit
8:30 am – 9:30 am Efficacious Verification of Loopback in PCIe (Jaydeep Suvariya)
9:30 am – 10:30 am  Advancing Artificial Intelligence and Machine Learning Applications (Vamshi Kandalla)
10:30 am – 11:00 am AM Break & Exhibit
11:00 am  – 12:00 pm  Cross-Layer Analysis and Debug of Power Management and Link Training (Patrick Connally) 
12:00 pm – 1:00 pm  Lunch & Exhibit 
1:00 pm – 2:00 pm Designing for Effective Use of PCIe 6.0 Bandwidth (Richard Solomon) 
2:00 pm – 3:00 pm PCI Express Protocol Compliance Troubleshooting and Debug (Gordon Getty) 
3:00 pm – 3:30 pm  PM Break & Exhibit 
3:30 pm – 4:30 pm Protecting Data over PCIe in High Performance Computing (Mike Borzaw) 
4:30 pm – 5:30 pm PCIe Advance Error Validation Methods (Vaibhav Vaidya) 

 

Speakers and Abstracts 

Mike Borza – Mike has more than 25 years of leadership and technology experience in security and safety critical systems engineering. He is Principal Security Technologist at Synopsys, specializing in design and development of security technologies for integrateed circuits. He was found and CTO of Elliptic Technologies, acquired by Synopsys in 2015. His previous experience includes Chrysalis-ITS (now Gemalto, a Thales Company), Ankari (now part of HID Global), and Alcatel Transport Automation. He has been an active contributor to the Security Tast Group of IEEE 802.1; was an editor of the 802.1AR Secure Device Identifier standard; was a founding member of the prpl Foundation and co-chair of its security engineering group; co-chairs of the EEMBC loT security benchmark working group; and is vice chair of the Accellera IP Security Assurance working group. Earlier in his career, he was involved in biometric identity management systems design, safety-critical systems engineering, and optoelectronics design and manufacturing. He holds more than 25 US patents, has authored many security articles and whitepapers, and is a frequent speaker on security at industry events around the globe. He is based in Ottawa, Canada.

Protecting Data over PCIe in High Performance Computing

When designing chips for data centers, the only way to keep cloud data safe is by protecting its confidentiality and integrity while in-motion and at-rest. This means that security solutions need be highly efficient, to support the rates of high-speed interfaces such as PCIe, with the lowest latency and minimum area impact. This presentation discusses how these security IP solutions integrated with the PCIe interface controllers make it faster and easier for designers to protect the SoCs against data tampering and physical attacks on every link while complying with the latest standards requirements.

Patrick Connally – Patrick is a Product Architect with the oscilloscope division at Teledyne LeCroy, and has been working on PCI Express technologies for 9 years. Patrick graduated from the National University of Ireland with a Bachelor’s degree in Electronic Engineering, and from Queens University Belfast with a PhD in Electrical Engineering.

Cross-Layer Analysis and Debug of Power Management and Link Training

When debugging PCI Express issues, it is important to be able to identify which layer is at fault to be able to find the root cause. PCI Express 5.0 supports several new features including 32GT/s data rate support, Precoding, and other Logical PHY and Data Link Layer changes. Power Management, Link Training and Equalization debug often involves cross-layer issues that can be challenging to debug and may require complex setups. This presentation will discuss how to simplify debug of Physical Layer issues that are indicated by Data Link Layer or Transaction Layer events.

Joe Cowan – Joe Cowan is a Senior Systems Architect in Hewlett Packard Enterprise.  He represents HPE in the PCIe Protocol Workgroup, where he's authored numerous ECNs and errata.  During his 43-year career with HP/HPE, Joe has worked in many other areas, including CXL, Gen-Z, InfiniBand, chipset/platform architecture, OS development, and security.

PCIe® 6.0 Protocol Update

This session covers PCI Express protocol developments over the last year or two, including completed ECNs, selected ECRs under development, and major protocol/spec changes in PCIe 6.0.  Completed ECNs include Combined Power and Relaxed Detect Timing.  Selected ECRs under development include TEE Device Interface Security Protocol (TDISP), DOE 1.1, CMA Update, ATS 2.0, and Unordered I/O (UIO).  Major protocol/spec changes for PCIe 6.0 include Flit Mode, Segment Support in Flit Mode, L0p replacing L0s in Flit Mode, Shared Flow Control Credits, 14-Bit Tags in Flit Mode, Max_Payload_Size enhancements, Deprecated features, and Improved SR-IOV spec integration.

PCIe 6.0 PHY Logical

PCI Express® (PCIe®) specification has been doubling the data rate every generation in a backwards compatible manner every two to three years. PCIe 6.0 specification has adopted PAM-4 signaling at 64.0 GT/s for maintaining the same channel reach as prior generations. A forward error correction (FEC) mechanism will offset the high BER of PAM-4. A new Flit-based approach with a light-weight, low-latency FEC coupled with a strong CRC and a low-latency link level retry mechanism in PCIe 6.0 specification meets the stringent low-latency, high bandwidth and high reliability goals. Shared credit pooling across multiple virtual channels is included to reduce the area and power overhead while providing the necessary quality of service guarantees. We also present a new low-power state (L0p) that ensures power consumption is proportional to bandwidth usage without impacting the traffic flow.

Gordon Getty – Gordon is Technical Marketing Manager at Teledyne LeCroy. He has been working on PCI Express technologies for 21 years. Gordon is an active contributor to the PCI Express Test Specifications. Gordon graduated from Glasgow University with a Bachelor’s degree in Electronics and Music and a MSc in Information Technology from the University of Paisle.

PCI Express Protocol Compliance Troubleshooting and Debug

This presentation discusses the requirements for PCI Express 4.0 and 5.0 Protocol compliance and how to debug and investigate issues that commonly arise during testing. Every component of PCIe Protocol compliance is discussed including Link and Transaction Layer, Retimer Logical, Lane Margining, and Configuration testing. Protocol Testing covers many different areas of the specification but many common issues can be resolved by paying attention to certain key areas prior to testing at a Compliance Workshop, helping to avoid delays in getting the device included on the Integrators List.

Vamshi Kandalla – A 25-year semiconductor and systems industry veteran, Vamshi Kandalla is Granite River Labs (GRL)'s Chief Strategy Officer. He leads strategic & commercial initiatives such as Imaging and Sensing, Photonics, Robotics, Security,  Charging, etc for the Automotive, Datacenters, Consumer and other emerging markets at GRL. He holds a Bachelor of Engineer degree.

Advancing Artificial Intelligence and Machine Learning Applications

PCI-SIG released the PCIe® 6.0 specification in early 2022, doubling the PCIe® 5.0 data rate to 64 GT/s (up to 256 GB/s with a x16 configuration). The PCIe® 6.0 technology adds innovative features like Pulse Amplitude Modulation with four levels (PAM4) signaling, low-latency Forward Error Correction (FEC), and Flit-based encoding to achieve high data transfer rates. The technology is an optimal solution for Artificial Intelligence and Machine Learning applications. Our presentation will cover PCIe® 6.0 architecture benefits for Artificial Intelligence & Machine Learning (AI/ML) workloads, PCIe® 6.0 technology impact on next-generation cloud data centers, and possible AI/ML use cases.

Mohiuddin Mazumder – Mohiuddin Mazumder is a Senior Principal Engineer in Data Center and AI division of Intel. He leads the Electrical pathfinding and Standards development work for high-speed differential interconnect technologies. He co-chairs the PCI-SIG Electrical WG and also leads the PCIe 5.0/6.0 Internal and External Cables specification for 32 and 64 GT/s.

PCIe 6.0 Electrical Update

In this presentation, we will provide an overview of updates to the specification of Reference Clock, Transmitter, Receiver, and Channel Compliance for PCIe 6.0 64 GT/s data rate. We will highlight the key improvements in circuit and channels required for achieving doubling of the data rate over PCIe 5.0.

Manisha Nilange  – Manisha Nilange is an I/O Architect, focusing on electrical compliance and enabling. She led development of PCIe 2.0 and 3.0 compliance test fixtures and subsequent industry enabling. Manisha has been with Intel Corporation since receiving her MS in Electrical Engineering from the University of Texas, Arlington.

PCIe CEM Updates 

This presentation provides updates on the PCI Express CEM specification development work in the PCI-SIG Electromechanical Workgroup. The presentation focuses on providing an overview of the changes introduced in PCI Express Card Electromechanical Specification, Rev 5.0 (CEM 5.0) and related ECRs. The presentation also provides an overview of several potential improvements under investigation for CEM 6.0. This includes Add-in Card outline updates, sideband interfaces and connector optimizations. 

PCIe Compliance Updates

The PCI-SIG has introduced the 5.0 Integrators List program with a new maximum data rate of 32 GT/s enabling a bi-direction link bandwidth up to 128 GB/s for a x16 link. The PCI Express Architecture PHY Test Specification Rev 5.0 has updated the 16 GT/s tests to support the faster rate and introduced new testing requirements including uncorrelated jitter and pulse width jitter for all 5.0 devices. Discussion of measurement methodologies for Tx Signal Quality and Link Equalization testing will provide insight into the latest measurement methodologies.

Richard Solomon – Richard Solomon is Technical Marketing Manager for Synopsys' PCIe Controller IP.  He’s been involved in PCI chip development since the original PCI spec, co-chairs the PCI-SIG compliance workgroup, and has served on the PCI-SIG Board of Directors for some 20 years. Richard holds a BSEE from Rice University and 27 US Patents, many PCI-related.

PCI Express Basics & Background 

In this session, attendees learn the basics of the PCI Express Architecture. This presentation covers the key features of PCI Express and provides an overview of the Electrical, Packet-based Protocol and Configuration Mechanism of this high-performance serial bus architecture. This session is geared towards attendees new to PCI Express Technologies. 

Designing for Effective Use of PCIe 6.0 Bandwidth

PCI Express 6.0 introduced 64GT/s signaling, bringing maximum PCIe bandwidth up to 256GB/s!  The sheer amount of data movement now possible offers architectural challenges beyond those arising “simply” from the doubling of clock speed or datapath width.  This presentation will discuss design choices and practices needed to make full use of that bandwidth across a variety of design points from x1 to x16 for both Endpoint and Root Port designs.  Various potential pitfalls and performance scenarios will be covered and data presented from actual early implementations. This presentation should be of interest to both experienced and new PCI Express designers.

Jaydeep Suvariya – Jaydeep Suvariya has completed his master’s engineering from Gujarat Technological University. He is working as an ASIC verification senior engineer in eInfochips an arrow company since the last 4 years. (Worked on- AHB, USB3.0, Synopsys PCIe-5.95a, PCIe 6.0, and CXL3.0 protocol) Prior to joining this organization, he has worked in ISRO.

Efficacious Verification of Loopback in PCIe

This paper elucidates a novel approach to verifying complex LTSSM Loopback state machines by using Rx Agent and Whitebox Model. By using this approach number of testcases is significantly reduced from 65 to 27, with this approach I’m able to hit the corner cases and find out the couple of Bugs that were not able to find out in Legacy testbench, Thus, the quality of IP is improved. By using this approach dependency on VIP for error Injection is removed so it further saves overall verification efforts, with this approach we can verify other LTSSM states and any new features quickly (Loopback – Loopback with Equalization). Resultantly, this approach minimizes verification engineer’s time and effort by 70%.

Vaibhav Vaidya – I am working as PCIe validation lead with 12 years of experience in PCIe electrical and protocol level validation using OS, BIOS and baremetal software development on ARM architecture.

PCIe Advance Error Validation Methods

PCIe and error injection on different operating system using actual hardware error injector is challenging and has cost barrier challenges in real world. This paper discussed PCIe AER validation using third party card and legacy error injection method using exerciser this enables to create real hardware event in different traffic scenarios and under different operating system environment.  This paper addresses AER and RAS validation methods and its comparison under different operating system environment using PCIe switch card, exerciser.