PCI-SIG Developers Conference 2017 Agenda

The sessions below are categorized by track subject according to the following key:

(1) PCI Express
(2) PCI-SIG Architecture
(3) Members Implementation
(4) Members Implementation

Day One - Wednesday, June 7, 2017
Time Title
8:00 am - 9:00 am
9:00 am - 9:30 am
Registration in Foyer
Introductory Keynote / Annual Members Meeting
9:30 am - 10:30 am (1) PCIe 4.0 Electrical Update    
(2) PCI-SIG Architecture Overview   
(3) PCIe Error Detection and Recovery Mechanisms  
(4) Challenges and Techniques for Implementing Lane Margining

10:30 am - 11:30 am

(1) PCIe CEM 4.0 Previews    
(2) PCIe Cable Update   
(3) PCI Express in Automotive Infotainment and ADAS Processors 
(4) PCI Express Link Training and Protocol Debug Techniques
11:30 am - 1:00 pm Lunch and Exhibit
1:00 pm - 2:00 pm (1) PCIe 4.0 PHY Logical
(2) PCI Express Basics    
(3) Refclk Fanout Best Practices for 8GT/s and 16GT/s Systems
(4) Jitter Measurements in the 0.7 4.0 PCI Express Base Specification
2:00 pm - 3:00 pm (1) PCIe Compliance Updates  
(2) PCIe Electrical Basics
(3) In-system Debugging of PCIe Devices 
3:00 pm - 3:30 pm PM Break and Exhibit
3:30 pm - 4:30 pm (1) PCIe 4.0 Protocol Update    
(2) M.2 Updates  
(3) Performance Tuning PCIe Systems
4:30 pm - 5:30 pm PCIe Panel Discussion
5:30 pm - 8:00 pm PCI-SIG 25th Anniversary Party
Day Two - Thursday, June 8, 2017
Time Title

 9:00 am - 10:00 am

(1) PCIe 4.0 Electrical Update    
(2) PCI-SIG Architecture Overview    
(3) Demystifying the PCIe Plug-Unplug  
10:00 am - 10:30 am AM Break and Exhibit
10:30 am - 11:30 am (1) PCIe CEM 4.0 Previews    
(2) PCIe Cable Update  
(3) Lessons Learned Bringing Up Early Adopter PCIe 4.0 Links 
11:30 am - 12:30 pm (1) PCIe 4.0 PHY Logical
(2) PCI Express Basics
(3) Multi-DMA Virtualization within Virtualized PCIe Systems
12:30 pm - 1:30 pm Lunch and Exhibit
1:30 pm - 2:30 pm (1) PCIe Compliance Updates
(2) PCIe Electrical Basics
(3) New Challenges in Compliance Test and Debug for PCIe 16GT/s
2:30 pm - 3:30 pm (1) PCIe 4.0 Protocol Update    
(2) M.2 Updates
(3) Verification Challenges for Retimers