Introduction

For nearly three decades, PCI Express® (PCIe®) technology has served as the de facto high bandwidth, low latency interconnect. As the industry evolves to meet the needs of data-intensive applications, the PCIe specification has kept pace, enabling future innovation.

We are pleased to commence 2022 on a high note with the official release of the PCI Express® (PCIe®) 6.0 specification to members.

Infographic of the PCIe 6.0 Architecture

By: Hope Bovenzi, Strategic Marketing, Astera Labs

With the widespread adoption of compute-intensive workloads – such as artificial intelligence and machine learning – in enterprise and cloud data centers, high-speed, low-latency interconnects like PCI Express^® architecture are required to connect high-performance nodes.

One of the many new features included in the PCI Express^® (PCIe^®) specification will be PAM4 (Pulse Amplitude Modulation with 4 levels) signaling.

PCI-SIG^® has shifted to virtual events for the 2020 calendar year and our first major members event was the Virtual PCI-SIG Developers Conference.

Earlier this month, I attended another eventful Flash Memory Summit (FMS) and I am pleased to say that PCI Express^® (PCIe^®) was around every corner at this year’s event.

Earlier this month, I attended another eventful Flash Memory Summit (FMS) and I am pleased to say that PCI Express^® (PCIe^®) was around every corner at this year’s event.

This year’s Flash Memory Summit (FMS) is coming up on August 6. As PCI Express technologies continue to evolve and make strides in the industry, PCI-SIG^® is excited to highlight our participation in the growth of flash storage.

This year’s Flash Memory Summit (FMS) is coming up on August 6. As PCI Express technologies continue to evolve and make strides in the industry, PCI-SIG^® is excited to highlight our participation in the growth of flash storage.

I am happy to share that PCI-SIG^® has begun developing the PCI Express^® (PCIe^®) 6.0 specification, targeted for release in 2021.

At PCI-SIG, we take pride in ensuring that our specifications operate without a hitch. However, sometimes PCI Express developers need to submit Engineering Change Requests (ECRs) to update parts of the specification so that PCIe integrated products can reach their optimal functionality.