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PCI-SIG® is excited to invite members back to our annual PCI-SIG U.S. Developers Conference (DevCon) in the Santa Clara Convention Center in Santa Clara, CA from June 13-14.
- PCI-SIG Membership
- Developers Conference
- PCI-SIG DevCon
- PCI-SIG
- PCI-SIG Membership
The PCI-SIG® Developers Conference returned to Taipei, Taiwan for the first time since 2019 on Feb. 20-21 at the Taipei Marriott Hotel. With 674 total attendees, it was the highest-ever turnout for a DevCon.
- Standards and Compliance
- Developers Conference
- PCI-SIG DevCon
- PCI-SIG Compliance
- PCI-SIG Integrators List
In early 2022, PCI-SIG® released the full version of the PCI Express® (PCIe®) 6.0 specification.
- Systems & Applications
- PCIe 6.0
- PAM4
- PAM4 signaling
- PCI Express 6.0
- PCI Express 6.0 Specification
- PCIe 6.0 architecture
Around the World with PCI-SIG: Join Us at the 2022 International DevCons
By Richard Solomon, PCI-SIG Vice President and Developers Conference Chair
- Standards and Compliance
- Developers Conference
- PCI-SIG DevCon
- PCI-SIG
- PCI-SIG Membership
By Scott Knowlton and Mihaela Erler, PCI-SIG MWG Co-Chairs
- Standards & Compliance
- Developers Conference
- PCI-SIG DevCon
- PCI-SIG
- PCI-SIG Membership
The PCI-SIG® Board of Directors honored three individuals for their years of service and contributions to the development and expansion of PCI Express® (PCIe®) technology during the PCI-SIG US DevCon 2022 on June 21-22 in
- Standards & Compliance
- Developers Conference
- PCI-SIG DevCon
- PCI-SIG
- PCI-SIG Membership
During the PCI-SIG® US DevCon 2022, the PCI-SIG Board of Directors surprised two individuals for their years of service and contributions to the development and expansion of PCI Express® (PCIe®) technology.
- Standards & Compliance
- Developers Conference
- PCI-SIG DevCon
- PCIe 6.0
- PCI Express 6.0
- PCI Express specification
Introduction
- Standards & Compliance
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe Storage
- PCI Express specification
- FLIT
- Forward Error Correct
For nearly three decades, PCI Express® (PCIe®) technology has served as the de facto high bandwidth, low latency interconnect. As the industry evolves to meet the needs of data-intensive applications, the PCIe specification has kept pace, enabling future innovation.
- Standards & Compliance
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe Storage
- PCI Express specification
- FLIT
- Forward Error Correct
We are pleased to commence 2022 on a high note with the official release of the PCI Express® (PCIe®) 6.0 specification to members.
- Standards & Compliance
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe Storage
- PCI Express specification
- FLIT
- Forward Error Correct
Infographic of the PCIe 6.0 Architecture
- Standards & Compliance
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe Storage
- PCI Express specification
- FLIT
- Forward Error Correction
I am excited to report that PCI-SIG has released PCIe 6.0 specification, version 0.9 to our members. This is a major milestone in our continued effort to double the data rate of the PCI Express® specifications while maintaining backwards compatibility.
- Standards & Compliance
- PCIe 6.0 specification
- PCIe 6.0
- PAM4
- PCIe FEC
- FLIT
- PCI Express specification
With the emergence of autonomous vehicles, AI-based advanced driver assistance systems (ADAS) and in-vehicle infotainment (IVI), today’s automobiles are becoming high-tech “servers on wheels.” PCI Express® (PCIe®) technology is expanding to become the interconnect of choice in automotive applicat
- Systems & Applications
- automotive
- PCIe
- PCI Express
- PCIe Retimer
- PCIe connectivity
- PCIe CEM
- PCIe Security
- PCIe low power
- PCI-SIG Automotive Taskforce.
The upcoming PCIe® 6.0 specification introduces Flow Control Unit (FLIT) encoding, which enables the specification to provide low latency with high efficiency. FLIT mode is adopted for the PCIe 6.0 architecture because error correction needs to operate on fixed sized packets.
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe FEC
- Forward Error Correction
- FLIT
By: Hope Bovenzi, Strategic Marketing, Astera Labs
- Signal Integrity
- automotive
- PCIe
- PCI Express
- PCIe Storage
- PCIe Retimer
- PCIe connectivity
- PCIe Bandwidth
- PCI-SIG Automotive Taskforce
Mohiuddin Mazumder of Intel was honored at this year’s PCI-SIG US DevCon
- Developers Conference
- PCI-SIG DevCon
- PCI-SIG
- PCI Express
Manisha Nilange of Intel was honored at this year’s PCI-SIG US DevCon
- Developers Conference
- PCI-SIG DevCon
- PCI-SIG
- PCI Express
With the widespread adoption of compute-intensive workloads – such as artificial intelligence and machine learning – in enterprise and cloud data centers, high-speed, low-latency interconnects like PCI Express® architecture are required to connect high-performance nodes.
- Standards & Compliance
- PCIe 4.0
- PCIe 5.0
- PCIe retimers
- PCIe redrivers
- PCIe 5.0 specification
The upcoming PCI Express® (PCIe®) 6.0 specification will continue PCI-SIG’s® longstanding history of innovation for the next generation of products to keep up with evolving needs in a wide range of markets.
- Systems & Applications
- PCIe 6.0
- PCI Express 6.0
- PCIe L0p
- PCIe low power state
One of the many new features included in the PCI Express® (PCIe®) specification will be PAM4 (Pulse Amplitude Modulation with 4 levels) signaling.
- Systems & Applications
- PCIe 6.0
- PCI Express 6.0
- What is PAM4
- PAM4
- PCIe FEC
- Forward Error Correction
For almost two decades, the PCI Express® (PCIe®) architecture has offered low latency and high bandwidth in support of next generation systems.
- Systems & Applications
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe FEC
- Forward Error Correction
- FLIT
We are starting 2020 with the release of version 0.5 of the PCI Express® (PCIe®) 6.0 specification incorporating the significant member feedback received on version 0.3.
- Standards & Compliance
- PCIe 6.0
- PCI Express 6.0
- PAM4
- PCIe FEC
- Forward Error Correction
- FLIT
- PCI Express specification
I’m happy to share that 2018 has been another productive year for PCI-SIG. In addition to significant progress in our specification development and compliance work, we also continued to provide educational resources to our members and the industry.
- Standards & Compliance
- PCI-SIG
- PCIe 5.0
- PCI Express 5.0
- OCP Summit
- Flash Memory Summit
- Developers Conference
By now, you probably know about the PCI-SIG Developers Conference which we hold in Santa Clara each year – a free event for our 750+ member companies with four tracks of presentations over two days.
- Standards & Compliance
- Technology
- PCI Express
- PCI-SIG
- Compliance
- Developers Conference
Press conference on June 5 to announce PCIe 5.0 spec updates
- Standards & Compliance
- PCI Express 5.0
- PCI-SIG
- PCIe 5.0
- Developers Conference
- Specification